A[0] = 1; Internal VDD regulator
0xAE = Sleep Mode ON (display OFF)
0xAF = Sleep Mode OFF (display ON)
1
1
0
A[0]
AE~AF
0
1
0
0
0
1
0
0
0
1
0
1
0
1
A0
X0
Set Sleep Mode
ON/OFF
Set Phase Length
A[3:0] = P1. Phase 1 period of 5‐31 DCLK clocks
A[7:4] = P2. Phase 2 period of 3‐15 DCLK clocks
9
7
0
1
0
1
B1
A[7:0]
B3
A[7:0]
1
A7
1
0
A6
0
1
A5
1
1
A4
1
0
A3
0
0
A2
0
0
A1
1
1
A0
1
A[3:0] = 0000; divide by 1
A[3:0] = 0001; divide by 2
A[3:0] = 0010; divide by 4
A[3:0] = 0011; divide by 8
0
Set Display Clock
Divide Ratio /
Oscillator
A7
A6
A5
A4
A3
A2
A1
A0
Frequency
A[3:0] = 0100; divide by 16
A[3:0] = 0101; divide by 32
A[3:0] = 0110; divide by 64
A[3:0] = 0111; divide by 128
A[3:0] = 1000; divide by 256
A[3:0] = 1001; divide by 512
A[3:0] = 1010; divide by 1024
A[3:0] >= 1011; invalid
A[7:4] = Set the Oscillator Frequency. Frequency increases with the
value of A[7:4]. Range 0000b~1111b.
A[1:0] = 00; GPIO0 input disabled
A[1:0] = 01; GPIO0 input enabled
A[1:0] = 10; GPIO0 output LOW
A[1:0] = 11; GPIO0 output HIGH
A[3:2] = 00; GPIO1 input disabled
A[3:2] = 01; GPIO1 input enabled
A[3:2] = 10; GPIO1 output LOW
A[3:2] = 11; GPIO1 output HIGH
Sets the second precharge period
A[3:0] = DCLKs
1100b
10b
Set GPIO
0
1
B5
A[3:0]
1
*
0
*
1
*
1
*
0
A3
1
A2
0
A1
1
A0
10b
1000b
Set Second
Precharge Period
Set Grayscale
Table
0
1
0
1
1
1
1
1
1
1
B6
A[3:0]
B8
A1[7:0]
1
*
1
A17
0
*
0
A16
1
*
1
A15
1
*
1
A14
0
A3
1
A13
A23
.
1
A2
0
A12
A22
.
1
A1
0
A11
A21
.
0
A0
0
A10
A20
.
Sets the gray scale pulse width in units of DCLK. Range 0‐180d.
A1[7:0] = Gamma Setting for GS1
A2[7:0] = Gamma Setting for GS2
.
.
.
A2[7:0]
A27
A26
A25
A24
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
A14[7:0] = Gamma Setting for GS14
A15[7:0] = Gamma Setting for GS15
A14[7:0] A147 A146 A145 A144 A143 A142 A141 A140
A15[7:0] A157 A156 A155 A154 A153 A152 A151 A150
Note: 0 < GS1 < GS2 < GS3 … < GS14 < GS15
The setting must be followed by command 0x00.
Sets Linear Grayscale table
GS0 pulse width = 0
GS0 pulse width = 0
Select Default
Linear Gray Scale
Table
0
B9
1
0
1
1
1
0
0
1
[13]