CHAPTER 1 INTRODUCTION
1.2 Features
{ Minimum instruction execution time: 50 ns (operation at main clock (fXX) = 20 MHz)
{ General-purpose registers: 32 bits × 32 registers
{ CPU features:
Signed multiplication (16 × 16 → 32): 1 to 2 clocks
(Instructions without creating register hazards can be continuously executed in parallel)
Saturated operations (overflow and underflow detection functions are included)
32-bit shift instruction: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
{ Memory space: 64 MB of linear address space
Memory block division function: 2 MB, 2 MB (Total of 2 blocks)
• Internal memory
µPD703212, 703212Y (Mask ROM: 64 KB/RAM: 4 KB)
µPD703213, 703213Y (Mask ROM: 96 KB/RAM: 4 KB)
µPD703214, 703214Y (Mask ROM: 128 KB/RAM: 6 KB)
µPD703215, 703215Y (Mask ROM: 256 KB/RAM: 16 KB)
µPD70F3214, 70F3214Y, 70F3214H, 70F3214HY (Flash memory: 128 KB/RAM: 6 KB)
µPD70F3215H, 70F3215HY (Flash memory: 256 KB/RAM: 16 KB)
• External bus interface
Separate bus/multiplex bus output selectable
8-/16-bit data bus sizing function
Wait function
• Programmable wait function
• External wait function
Idle state function
Bus hold function
{ Interrupts and exceptions
Non-maskable interrupts: 3 sources
Maskable interrupts:
35 sources (µPD703212, 703213, 703214, 70F3214, 70F3214H)
36 sources (µPD703212Y, 703213Y, 703214Y, 70F3214Y,
70F3214HY)
38 sources (µPD703215, 70F3215H)
39 sources (µPD703215Y, 70F3215HY)
32 sources
Software exceptions:
Exception trap:
Total: 84
1 source
{ I/O lines:
{ Key interrupt function
{ Timer function
16-bit timer/event counter P: 1 channel (µPD703215, 703215Y, 70F3215H, 70F3215HY only)
16-bit timer/event counter 0: 4 channels
8-bit timer/event counter 5: 2 channels
8-bit timer H:
2 channels
1 channel
8-bit interval timer BRG:
Watch timer/interval timer: 1 channel
Watchdog timers
Watchdog timer 1 (also usable as oscillation stabilization timer): 1 channel
Watchdog timer 2:
1 channel
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User’s Manual U16890EJ1V0UD
NEC [ NEC ]
