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UPD703208GKA-XXX-9EU 参数 Datasheet PDF下载

UPD703208GKA-XXX-9EU图片预览
型号: UPD703208GKA-XXX-9EU
PDF下载: 下载PDF文件 查看货源
内容描述: 32位单芯片微控制器产品 [32-Bit Single-Chip Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 757 页 / 4297 K
品牌: NEC [ NEC ]
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CHAPTER 2 PIN FUNCTIONS  
(ii) WR1 (upper byte write strobe) ... Output  
This is the write strobe signal output pin for the higher data of the external 16-bit data bus.  
(iii) RD (read strobe) ... Output  
This is the strobe signal that indicates that the bus cycle currently being executed is a read cycle for  
the external memory or external peripheral I/O. In the idle state (TI), this pin is inactive.  
(iv) ASTB (address strobe) ... Output  
This is the latch strobe signal output pin for the external address bus.  
The output becomes low level in synchronization with the falling edge of the clock in the T1 state of  
the bus cycle, and becomes high level in synchronization with the falling edge of the clock in the T3  
state.  
(11) PDL0 to PDL15 (Port DL) ... I/O  
Port DL is a 16-bit I/O port that can be set to input or output in 1-bit units.  
In addition to functioning as a port, PDL0 to PDL15 can also be used as an address/data bus (AD0 to AD15)  
when the memory is expanded externally in the control mode (external expansion mode).  
The port mode and control mode can be selected as the operation mode for each bitNote, and are specified by  
the port DL mode control register (PMCDL).  
Note When specifying the port mode/control mode (alternate function) for each bit, pay careful attention to  
the operation of the alternate functions.  
(a) Port mode  
PDL0 to PDL15 can be set to input or output in 1-bit units by the port DL mode register (PMDL).  
(b) Control mode  
PDL0 to PDL15 can be used as AD0 to AD15 with the PMCDL register.  
(i) AD0 to AD15 (address/data bus) ... I/O  
This is a multiplexed address/data bus during external access. In the address timing (T1 state), these  
pins function as 16-bit address A0 to A15 output pins, and in the data timing (T2, TW, and T3), they  
function as data I/O bus pins.  
(12) RESET (reset) ... Input  
RESET input is an asynchronous input, and when a signal that has a certain low-level width is input,  
regardless of the operation clock, system reset is executed with priority over all other actions.  
In addition to normal initialize and start, RESET can also be used to release the standby mode (HALT, IDLE,  
and STOP).  
(13) REGC (regulator control) ... Input  
This is the pin for connecting a capacitor for the regulator.  
(14) X1, X2 (crystal for main clock)  
These pins are used to connect the resonator that generates the main clock.  
An external clock can also be input.  
(15) XT1, XT2 (crystal for subclock)  
These pins are used to connect the resonator that generates the subclock.  
User’s Manual U15862EJ3V0UD  
72  
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