CHAPTER 2 PIN FUNCTIONS
(iv) TO51 (timer output) ... Output
This is the pulse signal output pin for the 8-bit timer.
(v) SO01 (serial output) ... Output
This is the serial transmit data output pin for CSI01.
(vi) SI01 (serial input) ... Input
This is the serial receive data input pin for CSI01.
(vii) SCK01 (serial clock) ... I/O
This is the serial clock I/O pin for CSI01.
(viii) INTP4 to INTP6 (interrupt request from peripherals) ... Input
These are the external interrupt request input pins.
(ix) KR6, KR7 (key return) ... Input
These are the key interrupt input pins. Their operations are specified by the key return mode register
(KRM) in the input port mode.
(8) PCM0 to PCM3 (port CM) ... I/O
Port CM is a 4-bit I/O port for which input or output can be set in 1-bit units.
In addition to functioning as a port, these pins can also be used for wait insertion signal input, internal system
clock output, and bus hold control signal I/O in the control mode.
The port mode and control mode can be selected as the operation mode for each bit, and are specified by the
port CM mode control register (PMCCM).
(a) Port mode
PCM0 to PCM3 can be set to input or output in 1-bit units by the port CM mode register (PMCM).
(b) Control mode
PCM0 to PCM3 can be set to the port mode or control mode in 1-bit units by the PMCCM register.
(i) WAIT (wait) ... Input
This is a control signal input pin that inserts data waits in a bus cycle. This pin supports
asynchronous input for CLKOUT. Sampling starts at the falling edge of the CLKOUT signal in the T2
and TW states of the bus cycle. If the setup/hold times in the sampling timing are not satisfied, wait
insertion may not be performed.
(ii) CLKOUT (clock output) ... Output
This is the internal system clock output pin. Since, in the single-chip mode, it is in the port mode
during the reset period, output is not performed from CLKOUT. To perform CLKOUT output, set this
pin to the control mode by the port CM mode control register (PMCCM).
(iii) HLDAK (hold acknowledge) ... Output
This is the output pin for the acknowledge signal that indicates that the V850ES/KF1 has received a
bus hold request and set the external address/data bus and the strobe pins to high impedance.
When this signal is active, the external address/data bus and the strobe pins are in high impedance,
and the bus mastership is handed to the external bus master.
User’s Manual U15862EJ3V0UD
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NEC [ NEC ]
