µPD31172
1. PIN FUNCTIONS
1.1 Pin Function List
(1) System bus interface signals
Signal Name
SCLK
I/O
I/O
Function
This is the SDRAM operating clock.
These form a 25-bit address bus.
These form a 32-bit data bus.
AD (0:24)
DATA (0:31)
LCDCS#
I/O
I/O
Input
This is the LCD chip select signal. This signal becomes active when the VR4121 accesses the
LCD using the AD or data bus.
RD#
I/O
I/O
• Output: This signal becomes active when the VRC4172 accesses SDRAM.
• Input: This signal becomes active when the VR4121 reads data from the VRC4172’s PCI
host bridge.
WR#
• Output: This signal becomes active when the VRC4172 writes data to SDRAM.
• Input: This signal becomes active when the VR4121 writes data to the VRC4172’s PCI host
bridge.
LCDRDY
Output
This is the LCD ready signal. This signal becomes active when a state is entered whereby the
VRC4172 can acknowledge an access to the LCD area from the VR4121.
ROMCS (2:3)#
CKE
I/O
I/O
This is an SDRAM chip select signal.
This is the SDRAM clock enable signal.
UUCAS#
ULCAS#
MRAS (0:1)#
UCAS#
I/O
This is an SDRAM DQM signal. This signal controls the I/O buffers for the DATA (24:31) pins.
This is an SDRAM DQM signal. This signal controls the I/O buffers for the DATA (16:23) pins.
This is an SDRAM chip select signal.
I/O
I/O
I/O
This is an SDRAM DQM signal. This signal controls the I/O buffers for the DATA (8:15) pins.
This is an SDRAM DQM signal. This signal controls the I/O buffers for the DATA (0:7) pins.
LCAS#
I/O
IOR#
Input
This is the system bus I/O read signal. This signal becomes active when any resource except
the USB inside the VRC4172 is accessed.
This is the system bus I/O write signal. This signal becomes active when any resource except
the USB inside the VRC4172 is accessed.
IOW#
Input
RESET
Input
Output
Output
Output
Input
This is the system bus reset signal.
IOCS16#
IOCHRDY
HOLDRQ#
HOLDAK#
SRAS#
This is the dynamic bus-sizing request signal.
This is the system bus ready signal.
This is the system bus access right request signal.
This is the system bus access enable signal.
I/O
This is the SDRAM RAS signal.
SCAS#
I/O
This is the SDRAM CAS signal.
BUSRQ (0:1)#
BUSAK (0:1)#
INTRP
Input
This is a signal input from the external bus master requesting access to the system bus.
This is a signal output to the external bus master permitting access to the system bus.
Output
Output
This is an interrupt request signal from the 16550 serial controller or the IEEE1284 parallel
controller.
IRQ
Output
This is an interrupt request signal from the general-purpose ports (GPIO (0:23)) or the
IEEE1284 parallel controller.
USBINT#
PS2INT
Output
Output
Input
This is an interrupt request signal from the USB host controller.
This is an interrupt request signal from the PS/2 controller.
This is the system bus clock.
BUSCLK
ARBCLKSEL
Input
This is a clock select signal for arbitrating the system bus (controls the HOLDRQ# signal)
(1: Internal clock used, 0: BUSCLK used)
8
Data Sheet U14388EJ2V0DS00
NEC [ NEC ]
