µPD31172
(b) Access to LCD area
Parameter
Command signal low-level width
Address setup time (to command signal)
Address hold time (from command signal)
LCDRDY valid delay time
LCDRDY set delay time
Symbol
tCLCH
tAVCL
tCHAV
tAVRH
tCLRL
tAVRZ
tDM
Conditions
MIN.
90
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
15
12
10
25
30
LCDRDY floating delay time
Data output hold time
6
Data output delay time
tDO
Data output valid time
tDV
10
10
10
Data input setup time
tDS
Data input hold time
tDH
(i) When accessing the internal PCI bus
AD (24:0)
(input)
LCDCS#
(input)
t
AVCL
t
CLCH
t
CHAV
RD#/WR#
(input)
t
AVRH
t
CLRL
t
AVRZ
LCDRDY
(output)
t
DS
t
DH
DATA (31:0)
(input)
t
DV
t
DM
DATA (31:0)
(output)
Remark The broken lines indicate high impedance
22
Data Sheet U14388EJ2V0DS00
NEC [ NEC ]
