µPD31172
(1) Clock parameters
Parameter
Symbol
fCLK
Conditions
MIN.
TYP.
48.0
MAX.
50.0
Unit
XIN48M clock frequency
MHz
(2) Reset parameters
Parameter
Symbol
tRST
Conditions
MIN.
30
MAX.
Unit
ns
RESET signal high-level width
USBRST# signal low-level width
tUSBRST
30
ns
(3) SDRAM interface parameters
Parameter
SCLK cycle
Symbol
tSCLK
tSCLKH
tSCLKL
tSDM
Conditions
MIN.
20.8
8
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCLK high-level width
SCLK low-level width
Data output hold time
Data output delay time
Data input setup time
Data input hold time
8
2
tSDO
15
tSDS
9.5
2
tSDH
t
SCLKH
t
SCLKL
t
SCLK
SCLK (I/O)
t
SDO
AD (24:0), WR#,
ROMCS (3:2)#,
t
SDM
UUCAS#, ULCAS#,
UCAS#, LCAS#,
MRAS (1:0)#, SRAS#,
SCAS#, CKE (I/O)
DATA (31:0) (output)
t
SDS
t
SDH
Hi-Z
Hi-Z
DATA (31:0) (input)
20
Data Sheet U14388EJ2V0DS00
NEC [ NEC ]
