CHAPTER 19 INSTRUCTION SET
Mnemonic
Operands
Byte
Clock
Operation
Flag
Z AC CY
SUBC
A, #byte
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
A, CY ← A − byte − CY
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
saddr, #byte
A, r
(saddr), CY ← (saddr) − byte − CY
A, CY ← A − r − CY
A, saddr
A, !addr16
A, [HL]
A, CY ← A − (saddr) − CY
A, CY ← A − (addr16) − CY
A, CY ← A − (HL) − CY
A, CY ← A − (HL + byte) − CY
A ← A byte
A, [HL+byte]
A, #byte
saddr, #byte
A, r
AND
(saddr) ← (saddr) byte
A ← A
r
A, saddr
A, !addr16
A, [HL]
A ← A (saddr)
A ← A (addr16)
A ← A (HL)
A, [HL+byte]
A, #byte
saddr, #byte
A, r
A ← A (HL + byte)
A ← A byte
OR
(saddr) ← (saddr) byte
A ← A
r
A, saddr
A, !addr16
A, [HL]
A ← A (saddr)
A ← A (addr16)
A ← A (HL)
A, [HL+byte]
A, #byte
saddr, #byte
A, r
A ← A (HL + byte)
A ← A V byte
XOR
(saddr) ← (saddr) V byte
A ← A V r
A, saddr
A, !addr16
A, [HL]
A ← A V (saddr)
A ← A V (addr16)
A ← A V (HL)
A, [HL+byte]
A ← A V (HL + byte)
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
User’s Manual U15075EJ1V0UM00
303
NEC [ NEC ]
