CHAPTER 19 INSTRUCTION SET
19.2 Operation List
Mnemonic
Operands
Byte
Clock
Operation
Flag
Z AC CY
MOV
r, #byte
3
3
3
2
2
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
2
2
2
1
1
2
6
6
6
4
4
4
4
4
4
8
8
6
4
4
6
6
6
6
6
6
4
6
6
6
8
8
8
r ← byte
saddr, #byte
sfr, #byte
A, r
(saddr) ← byte
sfr ← byte
A ← r
Note 1
Note 1
r, A
r ← A
A, saddr
saddr, A
A, sfr
A ← (saddr)
(saddr) ← A
A ← sfr
sfr, A
sfr ← A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
A ← (addr16)
(addr16) ← A
PSW ← byte
A ← PSW
PSW ← A
A ← (DE)
(DE) ← A
A ← (HL)
x
x
x
x
x
x
[DE], A
A, [HL]
[HL], A
(HL) ← A
A, [HL+byte]
[HL+byte], A
A, X
A ← (HL + byte)
(HL + byte) ← A
A ↔ X
XCH
Note 2
A, r
A ↔ r
A, saddr
A, sfr
A ↔ (saddr)
A ↔ sfr
A, [DE]
A ↔ (DE)
A ↔ (HL)
A ↔ (HL + byte)
A, [HL]
A, [HL+byte]
Notes 1. Except r = A.
2. Except r = A, X.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
User’s Manual U15075EJ1V0UM00
301
NEC [ NEC ]
