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MPD789871 参数 Datasheet PDF下载

MPD789871图片预览
型号: MPD789871
PDF下载: 下载PDF文件 查看货源
内容描述: 8位单芯片微控制器 [8-Bit Single-Chip Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 321 页 / 1339 K
品牌: NEC [ NEC ]
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CHAPTER 14 INTERRUPT FUNCTIONS  
Figure 14-13. Interrupt Request Acknowledgment Timing (Example: MOV A, r)  
8 clocks  
Clock  
Saving PSW and PC, and  
jump to interrupt servicing  
MOV A, r  
Interrupt servicing program  
CPU  
Interrupt  
If the interrupt request has generated an interrupt request flag (XXIF) by the time the instruction clocks under  
execution, n clocks (n = 4 to 10), are n 1, interrupt request acknowledgment processing will start following the  
completion of the instruction under execution. Figure 14-13 shows an example using the 8-bit data transfer  
instruction MOV A, r. Because this instruction is executed in 4 clocks, if an interrupt request is generated between  
the start of execution and the 3rd clock, interrupt request acknowledgment processing will take place following the  
completion of MOV A, r.  
Figure 14-14. Interrupt Request Acknowledgment Timing  
(When Interrupt Request Flag Is Generated in Final Clock Under Execution)  
8 clocks  
Clock  
Interrupt servicing  
program  
Saving PSW and PC, and  
jump to interrupt servicing  
NOP  
MOV A, r  
CPU  
Interrupt  
If the interrupt request flag (XXIF) is generated in the final clock of the instruction, interrupt request  
acknowledgment processing will begin after execution of the next instruction is complete.  
Figure 14-14 shows an example whereby an interrupt request was generated in the 2nd clock of NOP (a 2-clock  
instruction). In this case, the interrupt request will be processed after execution of MOV A, r, which follows NOP, is  
complete.  
Caution When interrupt request flag registers 0 and 1 (IF0 and IF1), or interrupt mask flag registers 0 and  
1 (MK0 and MK1) are being accessed, interrupt requests will be held pending.  
14.4.3 Multiple interrupt servicing  
Multiple interrupts, in which another interrupt request is acknowledged while an interrupt request being serviced,  
can be serviced using the priority order. If multiple interrupts are generated at the same time, they are serviced in  
the order according to the priority assigned to each interrupt request in advance (refer to Table 14-1).  
User’s Manual U15075EJ1V0UM00  
275  
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