K24C02C/K24C04/K24C08C/K24C16B
Two-wire Serial EEPROM
2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)
Bus Timing
Figure 10: SCL: Serial Clock, SDA: Serial Data I/O
tHIGH
tF
tR
tLOW
tLOW
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA_IN
tAA
tDH
tBUF
SDA_OUT
Write Cycle Timing
Figure 11: SCL: Serial Clock, SDA: Serial Data I/O
SCL
8th BIT
ACK
SDA
(1)
tWR
STOP
START
CONDITION
CONDITION
Note
1. The write cycle time tWR is the time from a valid stop condition
of a write sequence to the end of the internal clear/write cycle.
Spring 2011
.
011
.
V1.3
NEC [ NEC ]
