DDR3(L) 4Gb SDRAM
NT5CB(C)512M8DN / NT5CB(C)256M16DP
Change Frequency during Precharge Power-down
Previous Clock Frequency
New Clock Frequency
Te1
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Td0
Td1
Te0
tCKb
tCHb tCLb
tCK
CK
CK
tCH
tCL
tCKSRE
tCKSRX
CKE
tIH
tIS
tIS
tIH
tCPDED
tCKE
Command
Valid
Valid
MRS
NOP
NOP
NOP
NOP
NOP
NOP
tXP
DLL
Reset
Address
ODT
tAOFPD/tAOF
tIS
tIH
DQS,
DQS
High-Z
tDLLK
DQ
High-Z
DM
Enter Precharge
Power-Down mode
Exit Precharge
Power-Down mode
Frequency
Change
NOTES:
1. Applicable for both SLOW EXIT and FAST EXIT Precharge Power-down
2. tAOFPD and tAOF must be statisfied and outputs High-Z prior to T1; refer to ODT timing section for exact requirements
3. If the RTT_NOM feature was enabled in the mode register prior to entering Precharge power down mode, the ODT signal must
continuously be registered LOW ensuring RTT is in an off state. If the RTT_NOM feature was disabled in the mode register prior to entering
Precharge power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in this case.
Version 2.3
02/2017
41
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