NTC Proprietary
Level: Property
DDR3(L)-2Gb SDRAM
NT5CB(C)256M8JQ/NT5CB(C)128M16JR
Data Setup, Hold, and Slew Rate De-rating
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base)
and tDH(base) value to the delta tDS and delta tDH derating value respectively.
Example: tDS (total setup time) = tDS(base) + delta tDS
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and the
first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line
between shaded ‘Vref(dc) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the nominal
slew rate line anywhere between shaded ‘Vref(dc) to ac region’, the slew rate of the tangent line to the actual signal from
the ac level to dc level is used for derating value.
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the
first crossing of Vref(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal slew rate line between
shaded ‘dc level to Vref(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier than the nominal
slew rate line anywhere between shaded ‘dc to Vref(dc) region’, the slew rate of a tangent line to the actual signal from the
dc level to Vref(dc) level is used for derating value.
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac)
at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in the following tables, the derating values may be obtained by linear interpolation.
These values are typically not subject to production test. They are verified .
Derating values DDR3L-1600 tDS/tDH - AC/DC based AC135 Threshold
DDR3L Alternate AC135 Threshold -> VIH(AC)=VREF(DC)+135mV, VIL(AC)=VREF(DC)-135mV
DQS, Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH
2
68
45
45
30
68
45
45
30
68
45
45
30
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
53
38
-
-
1
0
0
0
0
0
0
8
8
16
16
-
-
-
-
-
DQ
Slew rate
V/ns
0.9
0.8
0.7
0.6
0.5
0.4
-
-
-
-
-
-
-
-
-
-
-
-
2
-
-3
-
2
3
-
-3
-8
-
10
11
14
-
5
1
-5
-
18
19
22
25
-
13
9
26
27
30
33
29
-
21
17
11
4
-
-
-
-
35
38
41
37
30
27
21
14
4
-
-
-
-
3
46
49
45
38
37
30
20
5
-
-
-
-
-4
-
-
-
-
-
-
-
-6
-
-
-
-
-
-
-
-
-
-11
NOTE1: Cell contents shaded in gray are defined as ‘not supported’.
Version 1.4
05/2019
148
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