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NT5CB128M16JR-DIH 参数 Datasheet PDF下载

NT5CB128M16JR-DIH图片预览
型号: NT5CB128M16JR-DIH
PDF下载: 下载PDF文件 查看货源
内容描述: [Automotive DDR3(L) 2Gb SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 154 页 / 4780 K
品牌: NANYA [ Nanya Technology Corporation. ]
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NTC Proprietary  
Level: Property  
DDR3(L)-2Gb SDRAM  
NT5CB(C)256M8JQ/NT5CB(C)128M16JR  
Input/Output Capacitance  
1600  
1866  
2133  
Unit  
Notes  
Parameter  
Symbol  
Min  
1.2  
Max  
2.3  
Min  
1.2  
Max  
2.2  
Min  
1.2  
Max  
2.1  
CIO  
(DDR3)  
CIO  
pF  
pF  
1,2,3  
1,2,3  
Input/output capacitance  
(DQ, DM, DQS, , TDQS,T)  
1.2  
2.2  
1.2  
2.1  
-
-
(DDR3L)  
CCK  
Input capacitance, CK and   
Input capacitance delta, CK and   
Input/output capacitance delta DQS  
and   
0.6  
1.4  
0.6  
1.3  
0.6  
1.3  
pF  
pF  
2,3  
CDCK  
0
0.15  
0
0.15  
0
0.15  
2,3,4  
CDDQS  
0
0.15  
1.3  
0
0.15  
1.2  
0
0.15  
1.2  
-
pF  
pF  
pF  
pF  
pF  
2,3,5  
2,3,6  
CI  
(DDR3)  
CI  
0.55  
0.55  
-0.4  
-0.4  
0.55  
0.55  
-0.4  
-0.4  
0.55  
-
Input capacitance,  
(CTRL, ADD,CMD input-only pins)  
1.2  
1.2  
2,3,6  
(DDR3L)  
Input capacitance delta,  
(All CTRL input-only pins  
CDI_CTRL  
0.2  
0.4  
0.2  
0.4  
-0.4  
-0.4  
0.2  
0.4  
2,3,7,8  
2,3,9,10  
Input capacitance delta,  
CDI_ADD_  
CMD  
(All ADD/CMD input-only pins)  
Input/output capacitance delta, DQ,  
DM, DQS, , TDQS, T  
Input/output capacitance of ZQ pin  
CDIO  
CZQ  
-0.5  
0.3  
-0.5  
0.3  
-0.5  
0.3  
pF  
pF  
2,3,11  
2,3,12  
-
3
-
3
-
3
NOTE 1. Although the DM, TDQS and T pins have different functions, the loading matches DQ and DQS  
NOTE 2. This parameter is not subject to production test. It is verified . The capacitance is measured according to  
JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)”) with VDD,  
VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, REET and ODT as necessary).  
VDD=VDDQ=1.5V, VBIAS=VDD/2 and ondie termination off.  
NOTE 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here  
NOTE 4. Absolute value of CCK-  
NOTE 5. Absolute value of CIO(DQS)-CIO()  
NOTE 6. CI applies to ODT, , CKE, A0-A14, BA0-BA2, RA, A, WE.  
NOTE 7. CDI_CTRL applies to ODT,  and CKE  
NOTE 8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(L))  
NOTE 9. CDI_ADD_CMD applies to A0-A14, BA0-BA2, RA, A and WE  
NOTE 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(L))  
NOTE 11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO())  
NOTE 12. Maximum external load capacitance on ZQ pin: 5 pF.  
Version 1.4  
05/2019  
118  
Nanya Technology Cooperation ©  
All Rights Reserved.  
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