N16D1625LPA
Enable Semiconductor Corp.
Functional Description
In general, this 16Mb SDRAM (512K x 16Bits x 2banks) is a dual-bank DRAM that operates at 2.5V and includes a synchronous
interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 8,388,608-bit banks is organized as
2,048 rows by 256 columns by 16-bits
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and
row to be accessed (A11 select the bank, A0-A10 select the row). The address bits (A11 select the bank, A0-A7 select the column)
registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device
initialization, register definition, command descriptions and device operation.
Power up and Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in
undefined operation. Once power is applied to VDD and VDDQ(simultaneously) and the clock is stable(stable clock is defined as a
signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command
other than a COMMAND INHIBIT or NOP. CKE must be held high during the entire initialization period until the RECHARGE command
has been issued. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND
INHIBIT or NOP commands should be applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE
command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is
ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to
applying any operational command. And a extended mode register set command will be issued to program specific mode of self
refresh operation(PASR). The following these cycles, the Low Power SDRAM is ready for normal operation.
Register Definition
Mode Register
The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst
length, a burst type, a CAS latency, an operating mode and a write burst mode. The mode register is programmed via the LOAD
MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS
latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 should be set to zero. M11 should be set
to zero to prevent extended mode register.
The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the
subsequent operation. Violating either of these requirements will result in unspecified operation.
Extended Mode Register
The Extended Mode Register controls the functions beyond those controlled by the Mode Register. These additional functions are
special features of the BATRAM device. They include Temperature Compensated Self Refresh (TCSR) Control, and Partial Array Self
Refresh (PASR) and Driver Strength (DS).
The Extended Mode Register is programmed via the Mode Register Set command (A11=1) and retains the stored information until it is
programmed again or the device loses power.
The Extended Mode Register must be programmed with M7 through M10 set to “0”. The Extended Mode Register must be loaded when
all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent
operation. Violating either of these requirements results in unspecified operation.
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Enable Semiconductor Corp. reserves the right to change products or specifications without notice.
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NANOAMP [ NANOAMP SOLUTIONS, INC. ]
