N16D1625LPA
Enable Semiconductor Corp.
Figure5: Mode Register Definition
A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
11
10
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
0
WB
CAS Latency
BT
Burst Length
0
0
0
M9
0
Write Burst Mode
M6 M5 M4 CAS Latency
M3 Burst Type
Burst Length
M3 = 0 M3 = 1
M2 M1 M0
Burst Read and Burst Write
Burst Read and Single Write
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
1
0
1
Sequential
Interleave
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
1
2
2
3
4
4
Reserved
Reserved
Reserved
Reserved
8
8
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
Note: M11(A11) must be set to “0” to select Mode Register (vs. the Extended Mode Register)
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is
selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
address, as shown in Table3.
Table 3: Burst Definition
Starting Column Order of Access Within a Burst
Burst
Length
Address
Note :
Sequential
Interleaved
A2
A1 A0
1. For full-page accesses: y = 256
2. For a burst length of two, A1-A7 select the block-
of-two burst; A0 selects the starting column within the
block.
0
1
0-1
1-0
0-1
1-0
2
0
0
1
1
0
1
0
1
0-1-2-3
0-1-2-3
3. For a burst length of four, A2-A7 select the block-
of-four burst; A0-A1 select the starting column within
the block.
1-2-3-0
2-3-0-1
3-0-1-2
1-0-3-2
2-3-0-1
4
3-2-1-0
4. For
a burst length of eight, A3-A7 select the
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Cn, Cn+1. Cn+2,
block-of-eight burst; A0-A2 select the starting column
within the block.
5. For a full-page burst, the full row is selected and A0-A7
select the starting column.
6. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
8
7. For a burst length of one, A0-A7 select the unique
column to be accessed, and mode register bit M3 is
ignored.
Full
n=A0-7
Cn+3, Cn+4…
…Cn-1, Cn...
Not Supported
Page
(Location 0-256)
7
Enable Semiconductor Corp. reserves the right to change products or specifications without notice.
Ver. A
NANOAMP [ NANOAMP SOLUTIONS, INC. ]
