N08L163WC1C
Advance Information
NanoAmp Solutions, Inc.
Timing Test Conditions
Item
0.1VCC to 0.9 VCC
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
1V/ns
0.5 VCC
CL = 50pF
-40 to +85 oC
Operating Temperature
Timing
55
Item
Symbol
Units
Min
Max
tRC
tAA
Read Cycle Time
Address Access Time (Random Access)
Chip Enable to Valid Output
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
55
25
55
tCO
tOE
Output Enable to Valid Output
Byte Select to Valid Output
tLB, tUB
tLZ
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Byte Select to Low-Z Output
10
5
tOLZ
tLBZ, tUBZ
tHZ
10
Chip Disable to High-Z Output
Output Disable to High-Z Output
Byte Select Disable to High-Z Output
Output Hold from Address Change
20
20
20
tOHZ
tLBHZ, tUBHZ
tOH
10
tWC
tCW
Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Byte Select to End of Write
Write Pulse Width
55
40
40
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAW
tLBW, tUBW
tWP
tAS
Address Setup Time
tWR
Write Recovery Time
0
tWHZ
tDW
Write to High-Z Output
Data to Write Time Overlap
Data Hold from Write Time
End Write to Low-Z Output
20
25
0
tDH
tOW
10
ns
Note:
1. Full device AC operation assumes a 100us ramp time from 0 to Vcc(min) and 200us wait time after Vcc stablization.
2. Full device operation requires linear Vcc ramp from VDR to Vcc(min) ≥ 100us or stable at Vcc(min) ≥ 100us.
Stock No. 23394-B 01/05
4
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NANOAMP [ NANOAMP SOLUTIONS, INC. ]
