NanoAmp Solutions, Inc.
Functional Block Diagram
N04L1618C2A
Word
Address
Inputs
Address
Decode
Logic
A0 - A3
Input/
Page
16K Page
x 16 word
x 16 bit
Address
Inputs
Output
Address
Decode
Logic
I/O0 - I/O7
Mux
A4 - A17
and
RAM Array
Buffers
I/O8 - I/O15
CE1
CE2
WE
OE
Control
Logic
UB
LB
Functional Description
1
CE1
CE2
WE
OE
UB
LB
MODE
POWER
I/O0 - I/O15
Standby2
Standby2
Standby2
Write3
H
X
X
L
X
L
X
X
X
L
X
X
X
X3
L
X
X
X
X
High Z
High Z
Standby
Standby
X
H
H
H
H
H
High Z
Standby
L1
L1
L1
L1
L1
L1
Active -> Standby4
Active -> Standby4
Standby4
Data In
Data Out
High Z
L
H
H
Read
Active
L
H
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7
are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown.
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
4. The device will consume active power in this mode whenever addresses are changed. Data inputs are internally isolated from
any expernal influence.
1
Capacitance
Item
Symbol
CIN
Test Condition
Min
Max
8
Unit
pF
VIN = 0V, f = 1 MHz, TA = 25oC
VIN = 0V, f = 1 MHz, TA = 25oC
Input Capacitance
I/O Capacitance
CI/O
8
pF
1. These parameters are verified in device characterization and are not 100% tested
(DOC# 14-02-016 REV G ECN# 01-1266)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NANOAMP [ NANOAMP SOLUTIONS, INC. ]
