Pin Descriptions
MU9C8338 10/100Mb Ethernet Filter Interface
PIN DESCRIPTIONS
Note: All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW.
Inputs should never be left floating. Refer to the Electrical Characteristics section for more information.
108
1
6
VDD
RP0
RP1
VDD
D15
NC
RP2
RP3
/RESET_LC
/W
/E
GND
RP4
102
/CM
/EC
RP5
GND
/MI
RP6
VDD
RP7
/FI
12
18
24
30
36
RP8
VDD
DQ0
DQ1
GND
DQ2
DQ3
DQ4
DQ5
VDD
DQ6
NC
96
RP9
RP10
RP11
RP12
GND
RP13
RP14
RP15
RP_DV
VDD
90
NC
DQ7
DQ8
DQ9
DQ10
GND
DQ11
DQ12
SC_ENB
TST_HLD
GND
84
78
TST_HLD2
NC
VDD
RP_NXT
DQ13
NC
RP_SEL
GND
NC
DQ14
DQ15
GND
SYSCLK
NC
NC
NC
GND
Figure 2: Pinout
MII Interface
RXD[3:0] (Receive Data, Input, TTL)
any other error that the PHY can detect, even if the MAC
is not capable of detecting that error (see Timing
Diagrams: Timing Data for RXD, RX_DV, and RX_ER).
RXD[3:0] is the 4-bit MII Receive Data nibble (see
Timing Diagrams: Timing Data for RXD, RX_DV, and
RX_ER).
RX_CLK (Receive Clock, Input, TTL)
RX_DV (Receive Data Valid, Input, TTL)
RX_CLK is the receive clock recovered from the data by
the PHY. It is equal to 25MHz in 100Base-X mode or
2.5MHz in 10Base-X mode.
Data Valid is on RX_DV; RX_DV is asserted by the PHY
at the beginning of the first nibble of the data frame and
deasserted at the end of the last nibble of the frame. It
indicates that the data is synchronous to RX_CLK and is
itself synchronous to the clock (see Timing Diagrams:
Timing Data for RXD, RX_DV, and RX_ER).
CRS (Carrier Sense, Input, TTL)
Carrier sense CRS indicates that the medium is active
(non-idle) and remains asserted during a collision. For Rx
or Tx: CRS is HIGH in 10/100Base-X half-duplex mode;
for Rx it is HIGH in repeater, full-duplex, and loopback
modes. CRS is not synchronized to RX_CLK.
RX_ER (Receive Error, Input, TTL)
RX_ER indicates a data symbol error in 100Mb/s mode or
Rev. 1a
3
MUSIC [ MUSIC SEMICONDUCTORS ]
