Timing Diagrams
MU9C8338 10/100Mb Ethernet Filter Interface
t6
t3
t11
t9
/PCS (/PCSS)
A[7:0]
t10
t8
t12
t13
PROC_RDY
D[15:0](write)
t7
t4
/WRITE (write)
SYSCLK
Figure 8: Host Processor Interface - Write Sequence
Result Port Interface
Table 33: Result Port Interface Timing Data
No.
16
17
18
19
20
21
22
23
Symbol
tNLSH
Parameter (ns)
Min
Max
Notes
RP_NXT deassert to RP_SEL assert
RP_SEL to RP(15:0) Valid
RP_NXT to RP(15:0) invalid
RP_NXT to RP_SEL deassert
RP_NXT to RP_DV deassert
RP_NXT to next Valid RP(15:0)
RP_NXT LOW Time
0
tSHRPV
tNHRPX
tNHSL
20
0
3*SYSCLK+5
tNHPDL
tNHRPnV
tNLNH
7*SYSCLK+10
7*SYSCLK
3*SYSCLK+5
3*SYSCLK+5
tNHNL
RP_NXT pulse width
RP_DV
16
17
RP_SEL
21
18
invalid
valid
RP[15:0]
RP_NXT
valid
22
23
Figure 9: Result Port - Additional Valid Data Packets
20
RP_DV
RP_SEL
RP[15:0]
RP_NXT
16
19
17
18
valid
invalid
22
23
Figure 10: Result Port - No Additional Valid Data Packets
Rev. 1a
23
MUSIC [ MUSIC SEMICONDUCTORS ]
