MU9C8328A Ethernet Interface
FUNCTIONAL DESCRIPTION
The MU9C8328A works with the MUSIC LANCAMs to
provide a complementary and versatile 10 MHz Ethernet
filtering solution for bridges, routers, and switches. Using
the serial NRZ data stream and clock available from many
Ethernet controller chips, the MU9C8328A parses the
incoming frame, finds the Start Delimiter, and forms the
Destination and Source addresses into 16-bit words for
relay to the LANCAM. After all three 16-bit DA segments
have been loaded into the LANCAM, an automatic compare
occurs between the incoming DA and the 48-bit MAC
addresses stored in the LANCAM. If a match is found, the
MU9C8328A is notified, and if Control register bit 5 is set
for negative filtering, the /REJECT line will be asserted if
Control register bit 3 is set. An interrupt can also be
generated over the /INT pin if Control register bit 8 is set.
Also, if Control register bit 0 is set, the Associated data in
segment 0 of the matching entry in the LANCAM will be
retrieved and stored in the Associated Data register for
reading by the host processor. If a match is not found on
the DA, and Control register bit 5 was set for positive
filtering, the /REJECT line will be asserted. An interrupt
can also be enabled for a no-match on a DA using Control
register bit 10.
After the DA filtering, the Source Address is loaded
into the LANCAM in three segments. Upon the last
SA load, an automatic compare again takes place. If
there is a match between the SA and an entry in the
CAM, and Control register bit 7 was set, an interrupt is
asserted. Positive and negative filtering on the SA is
also possible, set by Control register bit 4, and the /INT
pin may be asserted as well. In the case of a no-match
on an SA, the SA can be automatically “learned” (that
is, moved to the first empty location in the LANCAM) if
Control register bit 1 is set.
If a Loss of Carrier is detected by SERCLK staying LOW
for more than 16 SYSCLK cycles, an interrupt is triggered
if Control register bit 12 is set. This interrupt also activates
if a collision is detected.
The host processor can access the MU9C8328A internal
registers, shown in Table 1, at any time, even when a frame
is being processed. Access to the LANCAM through the
LANCAM access registers (04H to 07H) is arbitrated,
however, with the network having precedence. The host
processor can have control of the LANCAM by setting
the Network Enable bit in the Control register (bit 13) to a 0,
which will disable network filtering until it is returned to a 1.
While disabled, bit 14 in the Control register sets the
MU9C8328A to accept all frames by keeping /REJECT
HIGH, or to reject all frames by keeping /REJECT LOW.
Registers 04H through 07H give the host processor access
to the LANCAM for Command and Data Write and Read
cycles, with /EC HIGH or LOW. This is often needed for
housekeeping activities, such as preventing the LANCAM
from becoming full by aging out old entries based on time
stamps stored in the Associated data (Segment 0) of the
LANCAM memory.
Registers 08H holds the update Op-Code. This is 0300H
after reset to maintain compatibility with the MU9C8328.
To update a SA entry time stamp, the device must be
initialized to auto-learn in the Control register and 0328H
(MOV HM, CR) must be written to the update Op-Code
register. When filtering the SA, if it does not exist in the
CAM, the SA gets put into the next free address. If it already
has been entered in the CAM, just the time stamp bits are
updated with the value in the time stamp register.
Register 08H holds the update Op-Code, 09H is the Purge
Routine Op-Code register and 0AH is the Time Stamp
register. Writing a value to the TimeStamp register
initiates a Purge routine. The lower 8 bits written to the
Time Stamp register is the time stamp that will be purged.
The upper 8 bits written to the register will be the new
time stamp for data.
The /INT pin will go LOW at the end of the SA field to
indicate an interrupt for any of the reasons set in the Control
register. Reading the Status register to discover the nature
of the interrupt will take the /INT pin HIGH again. The
READY signal goes LOW after a host processor write to a
register or the LANCAM to indicate that the Write cycle
has begun and return HIGH after a fixed number of SYSCLK
cycles. It will also go LOW during a read from the LANCAM
and return HIGH when the data from the LANCAM is valid.
Since a network compare activity has precedence over a
host process access to the LANCAM, READY will stay
LOW until the network activity is complete and the
host-induced LANCAM read has completed.
Figure 1 shows a typical network filtering sequence, where
the MU9C8328A’s Control register was set to 2109H. This
setting enables network filtering, enables an interrupt for
a match found on the DA, enables negative filtering on
the DA (reject if a DA match is found), enables asserting
the /REJECT pin for compares on the DA, and enables
retrieving the Associated Data field from the matching
location in the LANCAM.
5
Rev. 0.8 Draft
MUSIC [ MUSIC SEMICONDUCTORS ]
