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MU9C8148-TCC 参数 Datasheet PDF下载

MU9C8148-TCC图片预览
型号: MU9C8148-TCC
PDF下载: 下载PDF文件 查看货源
内容描述: SRT接口 [SRT Interface]
分类和应用: 微控制器和处理器外围集成电路uCs集成电路uPs集成电路
文件页数/大小: 24 页 / 107 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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MU9C8148  
PIN DESCRIPTIONS (CONT’D)  
RXC  
(Receive Clock, Input, TTL)  
D15–D0  
(Data, Common I/O, TTL)  
The rising edge of RXC clocks the RXD data received by the  
TMS38053/4 from the Token Ring. The RXC clock is also used  
to generate the control signals to the LANCAM, and controls  
the internal operation of the MU9C8148.  
The Data pins transfer data between the Host Processor and  
the internal registers of the MU9C8148. The data pins are  
registered on the falling edge of /HBRDY in the Write mode,  
and are valid on the falling edge of /HBRDY in the Read mode,  
as shown in the Timing diagrams.  
/RDY  
(Ring Interface Ready, Input, TTL)  
/RS, /LDS  
(Read Strobe/Lower Data Strobe,  
Input, TTL)  
The /RDY pin is taken LOW by the TMS38053/4 to indicate the  
presence of received data. /RDY must be HIGH if the RXD data  
is not valid.  
In the Intel mode, this pin is /RS and is taken LOW to begin a  
read cycle to the Host Processor interface. Data on D(15-0) is  
valid when /HBRDY goes LOW. In the Motorola mode, this pin  
is /LDS for Host processor read and write cycles. The falling  
edge of /LDS or /UDS begins the cycle; data is strobed when  
/HBRDY goes LOW for a Write cycle, and is valid on D(15-0)  
when /HBRDY goes LOW for a Read cycle.  
MAC Interface:  
XMATCH  
(Match, Output, Three-state TTL)  
XMATCH goes HIGH in combination with XFAIL going LOW to  
indicate that the frame currently being received should be  
copied. If XFAIL is HIGH, XMATCH is forced LOW.  
/WS, /UDS  
(Write Strobe/Upper Data Strobe,  
Input, TTL)  
XFAIL, /FLUSH  
(FAIL/FLUSH, Output,  
Three-state TTL)  
In the Intel mode, this pin is /WS, and is taken LOW to begin a  
write cycle from the Host Processor interface. Data on D(15-0)  
is strobed into the MU9C8148 when /HBRDY goes LOW. In the  
Motorola mode, this pin is /UDS for Host processor read and  
write cycles. The falling edge of /LDS or /UDS begins the Write  
cycle; data is strobed when /HBRDY goes LOW for a Write  
cycle, and is valid on D(15-0) when /HBRDY goes LOW for a  
Read cycle.  
The function of this pin is defined by the Control register. If the  
MU9C8148 is connected to a TMS380CX6, this pin is defined  
as XFAIL, which goes HIGH when XMATCH goes LOW, to tell  
the TMS380CX6 to discard the frame and flush the receive  
buffer.  
Host Processor Interface:  
/HBRDY  
(Ready, Output, Three-state TTL)  
ALE, SRNW (Address Latch Enable/System Read  
Not Write, Input, TTL)  
/HBRDY goes LOW to indicate to the Host processor that a  
data transfer is completed for a Write cycle or that data is valid  
for a Read cycle. After the Host processor takes /RS, /WS, or  
/LDS and /UDS HIGH, the MU9C8148 takes /HBRDY HIGH.  
/HBRDY becomes three-state one RXC period after it goes  
HIGH, or when /CS goes HIGH.  
This pin is ALE when the MU9C8148 is used in the Intel mode.  
The falling edge of ALE latches the address on the address  
lines. If the MU9C8148 is in the Motorola mode, this pin  
becomes SRNW, and is HIGH for a Host Processor Read cycle  
and LOW for a Write cycle.  
/HBEN  
(Data Buffer Enable, Output, TTL)  
/CS  
(Chip Select, Input, TTL)  
/HBEN goes LOW to enable external bi-directional buffers, if  
are needed on the D15–D0 lines. /HBEN goes HIGH to disable  
the external buffers.  
/CS going LOW enables the Host Processor interface of the  
MU9C8148 for a Host Processor read or write. When /CS is  
HIGH, /HBRDY goes three-state and the Host Processor  
interface is disabled.  
/HBDIR  
(Data Buffer Direction, Output, TTL)  
/HBDIR controls the direction of data flow in external  
bi-directional buffers. /HBDIR goes LOW to enable data flowing  
to the MU9C8148 and HIGH to enable data coming from the  
MU9C8148 registers.  
A4–A0  
(Address, Input, TTL)  
The Address pins select the internal register for Host processor  
reads and writes. In the Intel mode, the Address pins are  
latched by the falling edge of ALE. In the Motorola mode, the  
Address pins must remain stable until the rising edge of /LD  
and /UDS, as shown in the Timing diagrams.  
/INT  
(Interrupt, Output, Open Drain)  
This pin goes LOW to notify the Host processor that the  
MU9C8148 is running an Instruction Buffer routine, therefore  
accessing the LANCAM. /INT will remain LOW as long the  
routine is running.  
Rev. 5.5 Draft web  
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