LIST-XL Family
SWITCHING CHARACTERISTICS (see note 3)
SWITCHING CHARACTERISTICS (SEE NOTE 3)
Cycle Time
-70
-90
No.
Symbol
Parameter
Min. Max. Min. Max Notes
1
t
Chip Enable Compare Cycle Time
70
90
ELEL
Short Cycle
15
35
55
15
25
50
75
15
4
4
4
t
2
Chip Enable LOW Pulse Width
Medium Cycle
Long Cycle
ELEH
3
4
5
6
t
Chip Enable HIGH Pulse Width
EHEL
t
Control Input to Chip Enable LOW Setup Time
Control Input from Chip Enable LOW Hold Time
Chip Enable LOW to Outputs Active
2
10
3
2
10
3
5
5
6
CVEL
t
ELCX
t
ELQX
Register Read
Memory Read
30
52
10
50
75
15
4,6
4,6
7
t
7
Chip Enable LOW to Outputs Valid
ELQV
8
t
Chip Enable HIGH to Outputs HIGH-Z
Data to Chip Enable LOW Setup Time
Data from Chip Enable LOW Hold Time
Chip Enable LOW to Full Flag Valid
Chip Enable HIGH to /MF, /MM Invalid
Chip Enable HIGH to /MF, /MMValid
Reset LOW Pulse Width
3
2
3
2
EHQZ
9
t
DVEL
10
11
12
13
14
t
10
10
ELDX
t
50
18
75
25
ELFFV
t
0
0
EHMFX
EHMFV
t
t
100
100
8
RLRH
Table 17: Switching Characteristics
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
-1.0 Volts for a duration of 10 ns measured at the 50% amplitude points for Input-only lines (see Figure 5 on page 19).
Common I/O lines are clamped, so that signal transients can not fall below -0.5 Volts.
Over ambient operating temperature range and Vcc(min.) to Vcc(max.).
See Table 6 on page 15.
Control signals are /W, and /CM.
With load specified in Figure 4 on page 19, Test Load A.
With load specified in Figure 4 on page 19, Test Load B.
/E must be HIGH during this period to ensure accurate default values in the configuration registers.
With output and I/O pins unloaded.
20
Rev. 3.1