Operational Characteristics
LIST-XL Family
The Memory Array
Memory Organization
occursduringDatawritestotheComparandormaskregisters
when the destination segment counter reaches the end count
set in the Segment Control register. If there was a match, the
secondcyclereadsstatusorassociateddata,dependingonthe
state of /CM. The minimum timings for the /E control signal
aregivenintheSwitchingCharacteristicssectiononpage18.
Note that at minimum timings the /E signal is
non-symmetrical,andthatdifferentcycletypeshavedifferent
timing requirements, as given in Table 6 on page 15.
The Memory array is organized into 64-bit words with each
wordhavinganadditionaltwovaliditybits(SkipandEmpty).
By default, all words are configured to be 64 CAM cells.
However,bits8-6oftheControlregistercandivideeachword
into a CAM field and a RAM field. The RAM field can be
assigned to the least-significant or most-significant portion
of each entry. The CAM/RAM partitioning is allowed on
16-bit boundaries, permitting selection of the configuration
shown in Table 7 on page 15, bits 8-6 (e.g., "001" sets the 48
MSBstoCAMandthe16LSBstoRAM).MemoryArraybits
designated as RAM can be used to store and retrieve data
associated with the CAM content at the same memory
location.
Compare Operations
During a Compare operation, the data in the Comparand
register is compared to all locations in the Memory array
simultaneously. Any mask register used during compares
mustbeselectedbeforehandintheControlregister.Thereare
two ways compares are initiated: Automatic and Forced
compares.
Memory Access
There are two general ways to get data into and out of the
memory array: directly or by moving the data through the
Comparand or mask registers.
Automaticcomparesperformacompareofthecontentsofthe
ComparandregisteragainstMemorylocationsthataretagged
as "Valid," and occur whenever the following happens:
Thefirstway,throughdirectreadsorwrites,issetupbyissuing
a Set Persistent Destination (SPD) or Set Persistent Source
(SPS) command. The addresses for the direct access can be
directly supplied; supplied from the Address register,
supplied from the Next Free Address register, or supplied as
the Highest-Priority Match address.Additionally, all the
direct writes can be masked by either mask register.
•
The Destination Segment counter in the Segment
Control register reaches its end limit during writes to
the Comparand or mask registers.
•
After a command write of a TCO CT is executed
(except for a software reset), so that a compare is
executed with the new settings of the Control register.
ForcedcomparesareinitiatedbyCMPinstructionsusingone
of the four validity conditions, V, R, S, and E. The forced
compare against "Empty" locations automatically masks all
64 bits of data to find all locations with the validity bits set
to"Empty,"whiletheotherforcedcomparesaremaskedonly
as selected in the Control register.
The second way is to move data via the Comparand or mask
registers. This is accomplished by issuing Data Move
commands(MOV).MovesusingtheComparandregistercan
also be masked by either of the mask registers.
I/O Cycles
TheLIST-XLsupportsfourbasicI/Ocycles:DataRead,Data
Write, Command Read, and CommandWrite.The type of
cycle is determined by the states of the /W and /CM control
inputs.Thesesignalsareregisteredatthebeginningofacycle
by the falling edge of /E. Table 2 on page 2 shows how the
/W and /CM lines select the cycle type.
INITIALIZING THE LIST-XL
Initialization of the LIST-XL is required to configure the
various registers on the device. Since a Control register reset
establishestheoperatingconditionsshowninTable4onpage
8, restoration of operating conditions better suited for the
application may be required after a reset, whether using the
Control Register reset or the /RESET pin. When the device
powersup,thememoryandregistersareinanunknownstate,
so the /RESET pin must be asserted to place the device in a
known state.
During Read cycles, the DQ15-0 outputs are enabled after
/E goes LOW. During Write cycles, the data or command to
be written is captured from DQ15-0 at the beginning of the
cyclebythefallingedgeof/E.Figures1and2onpage10show
ReadandWritecyclesrespectively.Figure3onpage10shows
typical cycle-to-cycle timing with the Match flag valid at the
end of the Comparand Write cycle. Data writes and reads to
thecomparand,maskregisters,ormemoryoccurinonetofour
16-bit cycles, depending on the settings in the Segment
Control register. The Compare operation automatically
Rev. 3.1
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