MU9C2480A/L
OPERATIONAL CHARACTERISTICS Continued
If the Full Flag is disabled through bit 12 and bit 11, the
device behaves as if it is full and ignores instructions to
Next Free address. Also, writes to the Page Address register
will be disabled. All other instructions operate normally.
Additionally, with the /FF disabled, /FF=/FI. Normal
operation of the device is with the /FF enabled. The Full
Flag Enable field has no effect on the /FL Status Register
bit. This bit always reflects the true state of the device.
Each of the two counters consists of a start limit, an end
limit, and the current count value that points to the
segment to be accessed on the next data cycle. The
current count value can be set to any segment, even if
it is outside the range set by the start and end limits.
The counters count up from the current count value to
the end limit and then jump back to the start limit. If the
current count is greater than the end limit, the current
count value will increment to three, then roll over to
zero and continue incrementing until the end limit is
reached; it then jumps back to the start limit.
The IEEE Translation control at bit 10 and bit 9 can be used
to enable the translation hardware for writes to 64-bit
resources in the device. When translation is enabled, the
bits are reordered as shown in Figure 2.
If a sequence of data writes or reads is interrupted, the
Segment Control register can be reset to its initial start limit
values by using an RSC instruction. After the LANCAM
is reset, both Source and Destination counters are set to
count from Segment 0 to Segment 3 with an initial value of 0.
Control Register bits 8–6 control the CAM/RAM
partitioning. The CAM portion of each word may be sized
from a full 64 bits down to 16 bits in 16-bit increments. The
RAM portion can be at either end of the 64-bit word.
Page Address Register (PA)
Compare masks may be selected by bit 5 and bit 4. Mask
Register 1, Mask Register 2, or neither may be selected to
mask compare operations. The address register behavior is
controlled by bit 3 and bit 2, and may be set to increment,
decrement, or neither after a memory access. Bit 1 and bit 0
set the operating mode: Standard as shown in Table 5a on
page 12, or Enhanced as shown in Table 5b on page 12. The
device will reset to the Standard mode, and follow the 1480
operating responses in Table 5a. When operating in
Enhanced mode, it is not necessary to unlock the daisy
chain with a NOP instruction before command or data writes
after a non-matching compare, as required in the Standard
mode.
The Page Address register is loaded using a TCO PA
instruction followed by a Command Write cycle of a user
selected 16-bit value (not FFFFH). The entry in the PA
register is used to give a unique address to the different
devices in a daisy chain. In a daisy chain, the PA value of
each device is loaded using the SFF instruction to advance
to the next device, shown in the “Setting Page Address
Register Values” section on page 15. A software reset (using
the Control register) does not affect the Page Address register.
Device Select Register (DS)
The Device Select register is used to select a specific (target)
device. The TCO DS instruction sets the 16-bit DS register
to the value of the following Command Write cycle. The
DS register can be read. A device is selected when its DS is
equal to its PA value. In a daisy chain, setting DS = FFFFH
will select all devices. However, in this case, the ability to
read information out of the device is restricted shown in
Tables 5a and 5b on page 12. A software reset (using the
Control register) does not affect the Device Select register.
Segment Control Register (SC)
The Segment Control register, as shown in Table 9 on page 22,
is accessed using a TCO SC instruction. On read cycles, D15,
D10, D5, and D2 will always read back as 0s. Either the
Foreground or Background Segment Control register will be
active, depending on which register set has been selected,
and only the active Segment Control register will be written to
or read from.
D Q15
D Q8 D Q7
D Q0
The Segment Control register contains dual independent
incrementing counters with limits, one for data reads and
one for data writes. These counters control which 16-bit
segment of the 64-bit internal resource is accessed during
a particular data cycle on the 16-bit data bus. The actual
destination for data writes and source for data reads (called
the persistent destination and source) are set independently
with SPD and SPS instructions, respectively.
D Q15
D Q8 D Q7
D Q0
Figure 2: IEEE 802.3/802.5 Format Mapping
Rev. 1a
8
MUSIC [ MUSIC SEMICONDUCTORS ]
