MU9C2480A/L
OPERATIONAL CHARACTERISTICS Continued
active after a reset. Having two alternate sets of registers
Control Register (CT)
The Control register is composed of a number of switches
that configure the LANCAM, as shown in Table 8 on page
21. It is written or read using a TCO CT instruction. If bit 15
of the value written during a TCO CT is a 0, the device is
reset (and all other bits are ignored). See Table 4 on page 10
for the Reset states. Bit 15 always reads back as a 0. A write
to the Control register causes an automatic compare to
occur (except in the case of a reset). Either the Foreground
or Background Control register will be active, depending
on which register set has been selected, and only the active
Control register will be written to or read from.
that determine the device configuration allows for a rapid
return to a foreground network filtering task from a
background housekeeping task.
Writing a value to the Control register or writing data to the
last segment of the Comparand or either mask register will
cause an automatic comparison to occur between the
contents of the Comparand register and the words in the
CAM segments of the memory marked valid, masked by
MR1 or MR2 if selected in the Control register.
Instruction Decoder
If the Match Flag is disabled through bit 14 and bit 13, the
internal match condition, /MA(int), used to determine a
daisy-chained device’s response is forced HIGH as shown
in Tables 5a and 5b on page 12, so that Case 6 is not
possible, effectively removing the device from the daisy
chain. With the Match Flag disabled, /MF=/MI and
operations directed to Highest-Priority Match locations are
ignored. Normal operation of the device is with the /MF
enabled. The Match Flag Enable field has no effect on the
/MA or /MM output pins or Status Register bits. These
bits always reflect the true state of the device.
The Instruction decoder is the write-only decode logic for
instructions and is the default destination for Command
Write cycles. If an instruction’s Address Field flag (bit 11)
is set to a “1,” it is a two-cycle instruction that is not
executed immediately. For the next cycle only, the data from
a Command Write cycle is loaded into the Address register
and the instruction then completes at that address. The
Address register will then increment, decrement, or stay at
the same value depending on the setting of Control Register
bits CT3 and CT2. If the Address Field flag is not set, the
memory access occurs at the address currently contained
in the Address register.
Vcc
Vcc
16
D Q15–0
/E
D Q15–0
/MI
/FI
/MI
/E
PLD
/W
/W
L AN C AM
LANCAM
/MA
/FF
/C M
/EC
/C M
/EC
/MF
D Q15–0
/E
/MI
/FI
/MI
/W
LANCAM
/MA
L AN C AM
/FF
/C M
/EC
/MF
/MI
LANCAM
/MA
/MI
D Q15–0
/E
/MI
/FI
/W
LANCAM
/MA
L AN C AM
SYSTEM F U L L
/FF
/C M
/EC
SYSTEM
SYSTE M MATC H
M ATCH
/MF
Figure 1a: Vertical Cascading
Figure 1b: External Prioritizing
Rev. 1a
7
MUSIC [ MUSIC SEMICONDUCTORS ]
