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MU9C2485A-90TCI 参数 Datasheet PDF下载

MU9C2485A-90TCI图片预览
型号: MU9C2485A-90TCI
PDF下载: 下载PDF文件 查看货源
内容描述: WidePort LANCAM㈢家庭 [WidePort LANCAM㈢ Family]
分类和应用: 局域网
文件页数/大小: 28 页 / 161 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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WidePort LANCAM® Family  
OPERATIONAL CHARACTERISTICS Continued  
SWITCHING CHARACTERISTICS (see Note 3)  
-90  
-12  
-50  
-70  
Cycle Time  
“A” Devices  
“L” Devices  
Available  
Not Available  
·
N/A  
· · · ·  
N/A  
· · ·  
Min  
120  
35  
Min  
50  
15  
30  
45  
5
Max  
No  
1
Symbol  
Max Min Max Min Max  
Notes  
Parameter (all times in nanoseconds)  
t
ELEL  
70  
15  
35  
55  
15  
0
90  
25  
50  
75  
15  
0
Chip Enable Compare Cycle Time  
t
2
ELEH  
4
4
4
Chip Enable LOW  
Pulse Width  
Short Cycle:  
Medium Cycle:  
Long Cycle:  
75  
100  
20  
t
3
4
EHEL  
Chip Enable HIGH Pulse Width  
Control Input to Chip Enable LOW  
Set-up Time  
t
0
0
CVEL  
5
5
t
15  
3
10  
3
5
ELCX  
10  
3
10  
3
Control Input from Chip Enable LOW  
Hold Time  
t
6
7
ELQX  
6
Chip Enable LOW to Outputs Active  
Chip Enable LOW to Outputs Valid  
t
70  
85  
20  
ELQV  
30  
40  
10  
30  
52  
10  
50  
75  
15  
4,6  
4,6  
7
t
3
0
3
0
8
9
EHQZ  
3
0
3
0
Chip Enable HIGH to Outputs High-Z  
Data to Chip Enable LOW Set-up Time  
t
DVEL  
t
15  
0
10  
0
10  
11  
ELDX  
10  
0
10  
0
Data from Chip Enable LOW Hold Time  
Full In Valid to Chip Enable LOW  
Set-up Time  
t
FIVEL  
t
8
12  
13  
14  
FIVFFV  
5
5
7
Full In Valid to Full Flag Valid  
Chip Enable LOW to Full Flag Valid  
Match In Valid to Chip Enable LOW  
Set-up Time  
t
90  
ELFFV  
35  
50  
75  
t
0
0
0
0
MIVEL  
0
0
0
0
t
15  
16  
17  
18  
19  
EHMFX  
Chip Enable HIGH to /MF, /MA, /MM Invalid  
Match In Valid to /MF Valid  
t
8
MIVMFV  
4
5
7
t
30  
30  
EHMFV  
16  
18  
16  
18  
25  
25  
Chip Enable HIGH to /MF Valid  
Chip Enable HIGH to /MA and /MM Valid  
Reset LOW Pulse Width  
t
EHMXV  
t
100  
50  
RLRH  
100  
100  
8
Notes:  
1. -1.0V for a duration of 10 ns measured at the 50% amplitude points for Input-only lines (Figure 8).  
2. Common I/O lines are clamped, so that signal transients cannot fall below -0.5V.  
3. Over Ambient Operating Temperature and Vcc(min) to Vcc(max).  
4. See Table 8.  
5. Control signals are /W, /CM, and /EC.  
6. With load specified in Figure 7, Test Load A.  
7. With load specified in Figure 7, Test Load B.  
8. /E must be HIGH during this period to ensure accurate default values in the configuration registers.  
9. With output and I/O pins unloaded.  
10. TEST1 and TEST2 may not be implemented on all versions of these products.  
25  
Rev. 2  
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