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MU9C1480A-70DC 参数 Datasheet PDF下载

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型号: MU9C1480A-70DC
PDF下载: 下载PDF文件 查看货源
内容描述: LANCAM A / L系列 [LANCAM A/L series]
分类和应用: 存储内存集成电路静态存储器双倍数据速率局域网
文件页数/大小: 32 页 / 332 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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LANCAM A/L series (not recommended for new designs)  
Operational Characteristics  
Table 4: Standard and Enhanced Mode Device Select Response  
Standard Mode  
Case  
Internal  
/EC(int)  
Internal  
/MA(int)  
External  
/MI  
Device Select  
Register  
Command  
Write1  
Data  
Write  
Command  
Read  
Data  
Read  
YES3  
YES3  
NO  
YES4  
YES4  
NO  
1
2
3
1
1
1
X
X
X
X
X
X
DS = FFFFH  
DS = PA  
NO  
YES  
NO  
NO  
YES  
NO  
DS FFFFH and  
DS PA  
NO5  
NO5  
YES5  
4
5
0
0
0
X
1
0
1
1
X
NO  
NO  
NO  
NO  
NO  
NO  
X
62  
YES3  
YES4  
0
X
YES  
Enhanced Mode  
Case  
Internal  
/EC(int)  
Internal  
/MA(int)  
External  
/MI  
Device Select  
Register  
Command  
Write1  
Data  
Write  
Command  
Read  
Data  
Read  
YES3  
YES3  
NO  
YES4  
YES4  
NO  
1
2
3
1
1
1
X
X
X
X
X
X
DS = FFFFH  
DS = PA  
NO  
YES  
NO  
NO  
YES  
NO  
DS FFFFH and  
DS PA  
YES3,6  
YES3,6  
YES3  
YES3,7  
YES3,7  
YES4  
NO5  
NO5  
YES5  
4
5
0
0
0
0
1
0
0
X
1
X
X
X
NO  
NO  
62  
YES  
Notes:  
1.  
Exceptions are:  
A) A write to the Device Select register is always active in all devices;  
B) A write to the Page Address register is active in the device with /FI LOW and /FF HIGH; and  
C) The Set Full Flag (SFF) instruction is active in the device with /FI LOW and /FF HIGH.  
If /MF is disabled in the Control register, Internal /MA is forced HIGH preventing a Case 6 response.  
2.  
3.  
4.  
5.  
This is NO for a MOV instruction involving Memory at Next Free address if /FI is HIGH or the device is full.  
This is NO if the Persistent Destination is Memory at Next Free address and /FI is HIGH or the device is full.  
For a Command read following a TCO NF instruction, this is YES if the device contains the first empty location in a daisy chain (i.e., /FI LOW and  
/FF HIGH) and NO if it does not.  
6.  
7.  
This is NO for a MOV or VBC instruction involving Memory at Highest-Priority match.  
This is NO if the Persistent Destination is Memory at Highest-Priority match.  
Status Register  
Comparand Register (CR)  
The 32-bit Status register, shown in Status Register Bits on  
page 24, is the default source for Command Read cycles.  
Bit 31 (internal Full flag) goes LOW if the particular  
device has no empty memory locations. Bit 30 is the  
internal Multiple Match flag, which goes LOW if a  
Multiple match was detected. Bit 29 and Bit 28 are the  
Validity bits, which reflect the validity of the last memory  
location read. After a reset, the Validity bits read 11 until a  
read or move from memory has occurred. The rest of the  
Status register down to bit 1 contains the Page address of  
the device and the address of the Highest-Priority match.  
After a reset or a no-match condition, the match address  
bits are all 1s. Bit 0 is the internal Match flag, which goes  
LOW if a match was found in this particular device.  
The 64-bit Comparand register is the default destination  
for data writes and reads, using the Segment Control  
register to select which 16-bit segment of the Comparand  
register is to be loaded or read out. The persistent source  
and destination for data writes and reads can be changed to  
the Mask registers or memory by SPS and SPD  
instructions. During an automatic or forced compare, the  
Comparand register is simultaneously compared against  
the CAM portion of all memory locations with the correct  
validity condition. Automatic compares always compare  
against valid memory locations, while forced compares,  
using CMP instructions, can compare against memory  
locations tagged with any specific validity condition.  
The Comparand register may be shifted one bit at a time to  
the right or left by issuing a Shift Right or Shift Left  
instruction, with the right and left limits for the  
wrap-around determined by the CAM/RAM partitioning  
12  
Rev. 1  
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