ADC-318, ADC-318A
APPLICATION
This device can be used in applications where 3 parallel
channels are synchronized. Conversion speed is the highest
in the de-multiplexed mode. It is difficult to control timing of
three channels at such a high speed. Two practical ways to
maintain timing for reading data into the system are given.
1. Clock output of one A/D is used in reading data of
other channels
Time delay of Clock Output and Output Data are
specified as:
Td clk (CLK OUT Delay) ; 4.5nSec min., 8.0nsec max.
Tdo2 (Output Data Delay); 6.5nSec min., 10nsec max.
These values apply over the operating temperature and
supply voltage ranges. Timing control of Tset (Setup Time)
seems to be very critical. It tends to lead by 0.5nsec as
temperature and supply voltages go lower. When A/D
converters for 3 channels are used on the same board,
temperature and supply voltages tend to change in the
same direction and effects caused by these changes
are negligible.
8-Bit, 120MHz and 140MHz Full-Flash A/D Converter
Tdclk and Tdo2 at Ta=25°C , +Vs=+5.0V are;
Td clk: 5.0nsec min., 7.5nsec max.
Tdo2: 7.0nsec min., 9.5nsec max.
So long as devices are located on the same board and take
power from the same source, 2.5nsec min. of setup time for
data reading can be secured even though temperature and
power supply voltages vary. A timing diagram at 140MHz
sampling rate is shown in Figure 4a.
2. To read output data of 3 channels into a gate array
Both output data lines and each clock output are read into
a gate array if the digital circuits after the A/D conversion
consist of one high speed gate array. An AND gate is
prepared to take the AND of each output signal which is
used for reading output data. The slowest rise time clock
determines the system clock. Thus adequate setup time is
secured. This method can be employed only when a high
speed gate array is used. The setup time is delayed by the
delay time of the AND gate. The use of a discrete IC gate is
not recommended because of its time delay characteristics.
See Figure 4b
A/D CLCK
Th reset
RSET
5.0nS
(4.5nS)
Td clck min.
7.5nS
(8.0nS)
CLK OUT
Td clck max.
7.0nS
(6.5nS)
Tdo2 min.
Tdo2 max.
OUTPUT
DATA (A, B)
14nS
9.5nS
(10nS)
Thold min. 6.5ns
Tset min. 2.5nS
*Values in parenthesis are for
the entire operating temperature
and operating power supply ranges
Figure 4a: Timing diagram 1
A/D CLCK
Th reset
RSET
5.0nS
(4.5nS)
Td clck min.
7.5nS
(8.0nS)
7.0nS
(6.5nS)
Tdo2 min.
Tdo2 max.
OUTPUT
DATA (A, B)
9.5nS
(10nS)
14nS
CLK OUT
Td clck max.
*Values in parenthesis are for
the entire operating temperature
and operating power supply ranges
GATE ARRAY CLK
(CLK OUT 1, CLK OUT 2, CLK OUT 3)
Tset min.
5.0nS+XnS
Thold min.
6.5nS–XnS
Figure 4b: Timing diagram 2
www.murata-ps.com
Technical enquiries
email: sales@murata-ps.com, tel:
+1 508 339 3000
MDA_ADC-318.B01
Page 6 of 8
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