ADC-318, ADC-318A
8-Bit, 120MHz and 140MHz Full-Flash A/D Converter
3ns min. 6ns max
N-1
ANALOG SIGNAL A
IN
T
PW1
A/D CLOCK
T
PW0
A DATA OUTPUT
N+1
Tdo2
2.0V
0.8V
2.0V
0.8V
N+2
T
ds
N
N+1
N+3
N+4
N+5
N+6
N+7
T
6.5ns min. 10ns max.
N+3
N+2
B DATA OUTPUT
Td clock
4.5ns min. 8ns max.
CLOCK OUT
Trh
RSET
0ns min.
Trs
3.5ns min.
Trh
2.0V
N
Tdo1
T+2ns max.
2.0V
0.8V
~
T
~
T
318
TPW1, min 3.2ns
TPW0, min 3.2ns
318A
3.0ns
3.0ns
RESET PERIOD
Trs
0.8V
Figure 3-1: Demultiplexed Data Output
(Select-Pin: +DVS or left open, 120MHz max. Clock Frequency)
T
ds
N-1
3ns min. 6ns max.
N
N+2
N+1
N+3
318
TPW1, min 3.2ns
TPW0, min 3.2ns
318A
3.0ns
3.0ns
ANALOG SIGNAL A
IN
T
PW
1
A/D CLOCK
T
T
PW
0
A DATA OUTPUT
N-4
2.0V
0.8V
2.0V
0.8V
N-3
N-2
N-1
N
B DATA OUTPUT
N-5
N-4
6.5ns min. 10ns max.
N-3
N-2
N-1
T
do2
CLOCK OUT
(inverted A/D CLOCK OUT)
2.0V
0.8V
T
d clock
RSET
4.5ns min. 8ns max.
Figure 3-2: Straight Data Output
(Select-Pin: DGND, 100MHz max. Clock Frequency)
A/D CLOCK
A/D CLOCK
RSET
CLOCK OUT 1
CLOCK OUT 1
DATA OUT 1
(A,B)
DATA OUT 1
(A,B)
CLOCK OUT 2
CLOCK OUT 2
DATA OUT 2
(A,B)
DATA OUT 2
(A,B)
A/D CLOCK
A/D CLOCK
ADC-318/318A
RSET
(1)
CLOCK OUT 1
8
8
CLOCK OUT 2
DATA 1 (A, B)
A/D CLOCK
A/D CLOCK
ADC-318/318A
RSET
(1)
CLOCK OUT 1
8
8
CLOCK OUT 2
(2)
8
8
DATA 2 (A, B)
DATA 1 (A, B)
A/D CLOCK
ADC-318/318A
A/D CLOCK
RSET
(2)
A/D CLOCK
8
8
DATA 2 (A, B)
ADC-318/318A
RSET
A/D CLOCK
RSET
Figure 3-3: Parallel Operation without RSET Pulse
Figure 3-4: Parallel Operation using RSET Synchronization
Technical enquiries
email: sales@murata-ps.com, tel:
+1 508 339 3000
www.murata-ps.com
MDA_ADC-318.B01
Page 5 of 8
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