ADC-207
7-Bit, 20MHz, CMOS Flash A/D Converters
9
8
13
12
CLOCK IN
4
5
0.01µF
10pF
GROUND
+5 VOLTS
11
CLOCK OUT
6
20k
1
2
3
Figure 3. Optional Pulse Shaping Circuit
USING TWO ADC-207’S FOR 8-BIT RESOLUTION
Two ADC-207’s (A and B) are cascadable for applications requir-
ing 8-bit resolution. The device A provides a typical 7-bit output. The
OVERFLOW signal of device A turns off device A and turns on the device B.
The OVERFLOW signal of device A is also used as MSB for 8-bit operation.
The device B provides the other seven bits from the input signal. Figure 4
shows the circuit connections for the application.
OVERFLOW
18
BIT 1 (MSB)
6
8
4
OPTIONAL
MIDSCALE
ADJUST
1
9
3
+V
DD
+REFERENCE
CS1
OF
B1
B2
B3
B4
CLOCK
CS2
–REFERENCE
B5
B6
B7
DIG GND
10
11
12
13
14
15
16
17
2
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8 (LSB)
BEAT FREQUENCY AND ENVELOPE TESTS
Figure 5 shows an actual ADC-207 plot of the Beat Frequency Test.
This test uses a 20MHz clock input to the ADC-207 with a 20.002MHz full-
scale sine wave input. Although the converter would not normally be used
in this mode because the input frequency violates Nyquist criteria for full
recovery of signal information, the test is an excellent demonstration of the
ADC-207’s high-frequency performance.
The effect of the 2kHz frequency difference between the input and the
clock is that the output will be a 2kHz sinusoidal digital data array which
"walks" along the actual input at the 2kHz beat note frequency. Any inabil-
ity to follow the 20.002MHz input will be immediately obvious by plotting
the digital data array. Further arithmetic analysis may be done on the data
array to determine spectral purity, harmonic distortion, etc. This test is an
excellent indication of:
1. Full power input bandwidth of all 128 comparators.
(Any gain loss would show as signal distortion.)
2. Phase response linearity vs. instantaneous signal magnitude.
(Phase problems would show as
improper codes.)
3. Comparator slew rate limiting.
Figure 6 shows an actual ADC-207 plot of the Envelope Test. This test
is a variation of the previous test but uses a 10.002MHz sinewave input to
give two overlapping cycles when the data is reconstructed by a D/A con-
verter output to an oscilloscope. The scope is triggered by the 20MHz clock
used by the A/D. Any asymmetry between positive and negative portions of
the signal will be very obvious. This test is an excellent indication of slew
rate capability. At the peaks of the envelope, consecutive samples swing
completely through the input voltage range.
+5V
+5.12
REFERENCE
IN
10
TURN
ANALOG INPUT
ANALOG GROUND
CLOCK IN
7
7
ANALOG GROUND
ANALOG IN
6
8
1
4
9
+5V
18
3
+REFERENCE
CS1
CLOCK
ANALOG INPUT
CS2
+V
DD
–REFERENCE
DIG GND
OF
B1
B2
B3
B4
B5
B6
B7
14
15
16
17
2
10
11
12
13
REFERENCE
GROUND
Figure 4. Using Two ADC-207’s for 8-Bit Operation
NOTE: The output data bit numbering is offset by a
bit to the device B’s output.
www.murata-ps.com
Technical enquiries
email: sales@murata-ps.com, tel:
+1 508 339 3000
MDA_ADC-207.B01
Page 4 of 6
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