ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Power Supply Voltage (+VDD)
Digital Inputs
Analog Input
Reference Inputs
Digital Outputs
(short circuit protected to ground)
Lead Temperature (10 sec. max.)
LIMITS
–0.5 to +7
–0.5 to +5.5
–0.5 to (+VDD +0.5)
–0.5 to +VDD
–0.5 to +5.5
+300
UNITS
Volts
Volts
Volts
Volts
Volts
°C
PHYSICAL/ENVIRONMENTAL
PARAMETERS
Operating Temp. Range, Case:
LC/MC Versions
MM/LM/QL Versions
Storage Temp. Range
Package Type
DIP
LCC
MIN.
TYP.
MAX.
UNITS
0
–55
–65
—
—
—
+70
+125
+150
°C
°C
°C
18-pin ceramic DIP
24-pin ceramic LCC
Functional Specifications
(Typical at +5V power, +25°C, 20MHz clock, +REFERENCE = +5V,
–REFERENCE = ground, unless noted)
ANALOG INPUT
Input Type
Input Range
(dc-20MHz)
Input Impedance
Input Capacitance
(Full Range)
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
Sample Pulse Width
(During Sampling Portion of Clock)
Reference Ladder Resistance
MIN.
0
—
—
TYP.
MAX.
UNITS
Single-ended, non-isolated
—
+5
Volts
1000
—
Ohms
10
—
pF
DIGITAL INPUTS
+3.2
—
—
—
12
225
—
—
±1
±1
—
330
—
+0.8
±5
±5
—
—
Volts
Volts
microamps
microamps
ns
Ohms
TECHNICAL NOTES
1. Input Buffer Amplifier – Since the ADC-207 has a switched capacitor type input, the input
impedance of the 207 is dependent on the clock frequency. At relatively slow conversion rates,
a general purpose type input buffer can be used; at high conversion rates DATEL recommends
either the HA-5033 or Elantec 2003. See Figure 2 for typical connections.
2. Reference Ladder – Adjusting the voltage at +REFERENCE adjusts the gain of the ADC-207.
Adjusting the voltage at –REFERENCE adjusts the offset or zero of the ADC-207. The midpoint
pin is usually bypassed to ground through a 0.1µF capacitor, although it can be tied to a precision
voltage halfway between +REFERENCE and –REFERENCE. This would improve integral linearity
beyond 7 bits.
3. Clock Pulse Width – To improve performance at Nyquist bandwidths, the clock duty cycle can
be adjusted so that the low portion of the clock pulse is 12ns wide. The smaller aperture allows
the ADC-207 to closely resemble an ideal sampler. See Figure 4.
4. At sampling rates less than 100kHz, there may be some degradation in offset and differential
nonlinearity. Performance may be improved by increasing the clock duty cycle (decreasing the
time spent in the sample mode).
CAUTION
Since the ADC-207 is a CMOS device, normal precautions against static electricity should be
taken. Use ground straps, grounded mats, etc. The Absolute Maximum Ratings of the device
MUST NOT BE EXCEEDED as irrevocable damage to the ADC-207 will occur.
Conversion Rate
➀
Harmonic Distortion
➁
(8MHz 2nd Order Harmonic)
Differential Gain
➂
Differential Phase
➂
Aperture Delay
Aperture Jitter
No Missing Codes
LC/MC grade
LM/MM grade
Integral Linearity
➃
Over Temperature Range
Differential Nonlinearity
Over Temperature Range
Power Supply Rejection
Data Coding
Data Output Resolution
Logic Levels
Logic "1"
Logic "0" (at 1.6mA)
Logic Loading "1"
Logic Loading "0"
Output Data Valid Delay
(From Rising Edge)
PERFORMANCE
20
25
—
—
—
—
—
0
–55
—
—
—
—
—
DIGITAL OUTPUTS
7
+2.4
—
–4
+4
—
–40
3
1.5
8
50
—
—
±0.8
±1
±0.3
±0.4
±0.02
—
—
—
—
—
—
+70
+125
±1
—
±0.5
±0.6
—
MHz
dB
%
degrees
ns
ps
°C
°C
LSB
LSB
LSB
LSB
%FSR/%Vs
0.1µF
+5V
20MHz
CLOCK
+15
47µF
4.7µF
+
0.01µF
+
+5V
1
2
12
5
HA-5033
10
6
47µF
7
11
10
W
3
4
5
CLOCK
DIGITAL GND
–REFERENCE
V
IN
MID
+REFERENCE
ANALOG GND
+V
DD
B7
B6
18
17
16
15
B7 (LSB)
B6
B5
B4
B3
B2
11
B1 (MSB)
10
OF
B5
14
B4
13
B3
B2
B1
OF
12
Straight binary
—
—
0.1µF
8
CS1
9
CS2
Bits
Volts
Volts
mA
mA
ns
0.1µF
+
–15
+4.5
—
—
—
15
—
+0.4
—
—
17
Figure 2. Typical Connections for Using the ADC-207
POWER REQUIREMENTS
Power Supply Range
(+V
DD
)
+3.0
+5.0
+5.5
Volts
Power Supply Current
—
+50
+70
mA
Power Dissipation
—
250
385
mW
Footnotes:
➀
At full power input and chip selects enabled.
➁
At 4MHz input and 20MHz clock.
➂
For 10-step, 40 IRE NTSC ramp test.
➃
Adjustable using reference ladder midpoint tap. See ADC-207 Operation.
MURATA-PS [ MURATA POWER SOLUTIONS INC. ]
