NB650/NB650H – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
1
VREF
+
VRAMP
current of the converter. The input ripple current
can be estimated as:
(23)
(24)
2
R2A =
1
1
×(VOUT1 − VREF
−
VRAMP
)
VOUT
VOUT
R1
2
ICIN = IOUT
×
×(1−
)
(26)
V
V
IN
IN
1
1
R2B =
The worst-case condition occurs at:
IOUT
(VOUT2 − VREF
−
VRAMP )
1
1
2
×
−
ICIN
=
1
2
(27)
R1
R2A
VREF
+
VRAMP
2
For simplification, choose an input capacitor
whose RMS current rating is greater than half of
the maximum load current.
(25)
1
R2C =
1
2
(VOUT3 − VREF
−
VRAMP )
1
1
×
−
The input capacitance value determines the input
voltage ripple of the converter. If the system
requires a specific input voltage ripple, choose
the input capacitor that meets the specification.
1
R1
R2A
VREF
+
VRAMP
2
Select CDC>10×C4 for better DC blocking, but
select a value less than 0.47µF when considering
start up performance. For larger CDC values for
better FB noise immunity, combine with reduced
R1 and R2 to limit the CDC to a reasonable value
without affecting system start-up. Note that even
with CDC, the load and line regulation are still
The input voltage ripple can be estimated as:
IOUT
VOUT
VOUT
ΔV =
×
×(1−
)
(28)
IN
fSW × CIN
V
V
IN
IN
The worst-case condition occurs at VIN = 2VOUT
,
related to VRAMP
.
where:
IOUT
1
4
ΔV =
×
(29)
IN
fSW × CIN
Output Capacitor
The output capacitor maintains the DC output
voltage. Use ceramic or POSCAP capacitors.
The output voltage ripple can be estimated as:
VOUT
V
1
×(1− OUT )×(RESR
+
(30)
)
ΔVOUT
=
Figure 11: Simplified Circuit with Ceramic DC-
Blocking Capacitor
fSW ×L
V
8× fSW × COUT
IN
Where RESR is the equivalent series resistance
(ESR) of the output capacitor.
Input Capacitor
The input current to the step-down converter is
discontinuous, and therefore requires a capacitor
to supply the AC current to the step-down
converter while maintaining the DC input voltage.
Use ceramic capacitors for best performance.
The capacitance varies significantly over
temperature. Capacitors with X5R and X7R
ceramic dielectrics are recommended because
they are fairly stable over temperature.
For ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency, and causes the majority of the output
voltage ripple. For simplification, the output
voltage ripple can be estimated as:
VOUT
VOUT
ΔVOUT
=
×(1−
)
(31)
8× fSW2 ×L×COUT
V
IN
The output voltage ripple caused by ESR is very
small, and therefore requires an external ramp to
stabilize the system. The external ramp can be
generated through resistor R4 and capacitor C4
following equations 5, 9 and 10.
In the layout, place the input capacitors as close
to the IN pin as possible.
The capacitors must also have a ripple current
rating greater than the maximum input ripple
voltage generated from the ESR is high enough
to stabilize the system. Therefore, an external
For POSCAP capacitors, the ESR dominates the
impedance at the switching frequency. The ramp
NB650/NB650H Rev. 1.12
10/11/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
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