NB650/NB650H – 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS
APPLICATION INFORMATION
Setting the Output Voltage-Large ESR Caps
Choose R1 within 5kꢀ-to-100kꢀ. The value of
R2 then is determined as follows:
A resistor divider from the output voltage to the
FB pin sets the output voltage. Changing the VID
codes for the NB650/NB650H accomplishes the
same thing.
VFB(AVG)
(18)
R2A =
1
1
(
+
)×(VOUT1 − VFB(AVG) )
R1 R4+R9
(19)
(20)
1
When there is no external ramp, the output
voltages are set by feedback resistors R1 and
R2A, R2B and R2C. First, choose R1 within 5kꢀ-
to-100kꢀ to ensure stable operation. VOUT1, VOUT2
R2B =
R2C =
VOUT2 − V
FB(AVG) ×(
VFB(AVG)
1
1
1
+
) −
R1 R4+R9 R2A
,
1
VOUT3 and VOUT4 are the voltages at different VID
VOUT3 − V
FB(AVG) ×(
VFB(AVG)
1
1
1
codes, arranged from low to high. Then
determine R2A, R2B and R2C as follows:
+
) −
R1 R4+R9 R2A
VREF
And VOUT4 also can be calculated with equation
17.
(14)
(15)
R2A =
×R1
VOUT1 − 21 ΔVOUT − VREF
The VFB(AVG) is the average value on FB. VFB(AVG)
varies with the VIN, VO, and load condition; its
value in skip mode is lower than in PWM mode,
which means the load regulation is strictly related
to the VFB(AVG). Also the line regulation is related
to the VFB(AVG); use a lower VRAMP that meets the
conditions of equation 10 for better load or line
regulation.
1
R2B =
VOUT2
−
21 ΔVOUT2 − VREF
1
1
×
−
VREF
R1 R2A
(16)
1
21 ΔVOUT3 − VREF
VREF
R2C =
VOUT3
−
1
1
×
−
R1 R2A
For PWM operation, estimate VFB(AVG) from the
following equation:
VOUT4 can be calculated as:
VREF ×(R1+ R2A //R2B//R2C)
1
1
2
R1//R2
RAMP× R1//R2+R9
(17)
+ 2 ΔVOUT4
VOUT4
=
(21)
VFB(AVG) = VREF
+
V
R2A //R2B//R2C
Where ΔVOUTx is the output ripple determined by
equation 30.
Usually, R9 is set to 0ꢀ, and it can also be set
following equation 22 for better noise immunity.
Set the value to <(1/5)×R1//R2 to minimize its
Setting the Output Voltage-Small ESR Caps
influence on VRAMP
.
1
(22)
R9 ≤
2π× C4× 2fSW
Using equations 18 through 20 to calculate the
output voltage can be complicated. Furthermore,
as VRAMP changes due to changes in VOUT and VIN,
VFB also varies. To improve the output voltage
accuracy and simplify the R2A, R2B and R2C
calculations, add a DC-blocking capacitor (CDC)
to filter the DC influence from R4 and R9. Figure
11 shows a simplified circuit with external ramp
compensation and a DC-blocking capacitor. The
addition of this capacitor simplifies the R2A, R2B
and R2C calculations, as per equations 23-25.
Figure 10: Simplified Ceramic Capacitor Circuit
When using a low-ESR ceramic capacitor on the
output, add an external voltage ramp to FB
through resistor R4 and capacitor C4. The ramp
voltage, VRAMP, influences the output voltage
besides the resistor divider shown in Figure 10.
Equation 7 calculates VRAMP
.
NB650/NB650H Rev. 1.12
www.MonolithicPower.com
14
10/11/2012
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