TM
MP6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT
APPLICATION INFORMATION
connects to the SENSE pin. The circuit can be
used to monitor any voltage higher than 0.4V.
Reset Output Function
RESET
The MP6400
output is typically connected
RESET
VSEN
to the
input of a microprocessor, as shown
VOUT
RESET
in Figure 3. When
is not asserted, a pull
VCC
up resistor must be connected to hold this signal
high. The voltage of reset signal is allowed to be
higher than VCC (up to 6V) through a resistor
R1
= (1+
)
0.4
VIT
R2
R1
R2
MP6400DJ-01
RESET
pulling up from supply line. If the voltage is below
RESET
0.8V,
output is undefined. This condition
SENSE
GND
can be ignored generally because that most
microprocessors do not function at this state.
1nF
MR
When both SENSE and
are higher than their
RESET
threshold voltage,
output holds logic high.
Figure 4—MP6400DJ-01 Monitoring a User-
Defined Voltage
Once either of the two drops below their
RESET
threshold,
will be asserted.
VCC
Monitor Multiple System Voltages
MR
The manual reset (
) can introduce another
MR
RESET
R1
VCC
logic signal to control the
. When
is a
Microprocessor
DSP
RESET
logic low (0.25VCC),
MR
will be asserted. After
are above their thresholds,
SENSE
100k
both SENSE and
RESET
Microcontroller
will be driven to a logic high after a reset
0.1uF
1nF
R2
MR
MR
delay time. The
is internally connected to VCC
through a 90kΩ resistor so this pin can float. See
how multiple system voltages are monitored by
RESET
RESET
GND
47pF
CDELAY
GND
MR
MR
CDELAY
in Figure 5. If the signal on
isn’t up to VCC,
there will be an additional current through internal
90kΩ pull up resistor. A logic-level FET can be
used to minimize the leakage, as shown in Figure
6.
Figure 3—Typical Application of MP6400 with
Microprocessor
MR
From the point that
is again logic high and
3.3V
1.2V
SENSE is above VIT + VHYS (the threshold
RESET
hysteresis),
will be driven to a logic high
after a reset delay time. The reset delay time is
VCORE
VI/O
SENSE VCC
SENSE VCC
programmable by CDELAY pin. Due to the finite
RESET
impedance of
pin, the pull up resistor
MP6400DJ-33
DSP
MP6400DJ-12
should be bigger than 10kΩ.
MR
RESET
RESET
RESET
Monitor a Voltage
The SENSE input pin is connected to the
monitored system voltage directly or through a
CDELAY
GND
CDELAY
GND
GND
resistor network (on MP6400DJ-01). When the
RESET
voltage on the pin is below VIT,
is asserted.
Figure 5— MP6400 Family Monitoring Multiple
System Voltages
A threshold hysteresis will prevent the chip from
responding perturbation on SENSE pin. A 1nF to
10nF bypass capacitor should be put on this pin
to increase its immunity to noise. A typical
application of the MP6400DJ-01 is shown in
Figure 4. Two external resistors form a voltage
divider from monitored voltage to GND. Its tap
MP6400 Rev. 1.0
9/7/2012
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