TM
MP6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT
FUNCTIONAL BLOCK DIAGRAM
VCC
VCC
VCC
VCC
90k
MP6400DJ-01
Adjustable Voltage
MP6400DJ-XX
90k
RESET
RESET
MR
MR
0.4V
SENSE
--
+
R1
R2
Reset
Logic
Timer
Reset
Logic
Timer
+
--
0.4V
SENSE
CDELAY
CDELAY
GND
Adjustable Voltage Version
GND
Fixed Voltage Version
Figure 1—Functional Block Diagram
TIMING DIAGRAM
VCC
0.8V
0.0V
RESET
tD
tD
tD
tD=Reset Delay
=Undefined State
SENSE
VIT+VHYS
VIT
MR
0.7VCC
0.25VCC
Time
Figure 2—MP6400 Timing Diagram
TRUTH TABLE
SENSE > VIT
MR
RESET
L
0
1
0
1
L
L
L
L
H
H
H
MP6400 Rev. 1.0
9/7/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
8
MPS [ MONOLITHIC POWER SYSTEMS ]
