MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS
With all boost regulators the right half plane
zero (RHPZ) is given in hertz by:
For the negative linear regulator:
1
fNEGPOLE1
2
2 R7 R5 C9
VIN
VMAIN
VMAIN
1
fRHPZ
fNEGZERO1
2 ILOAD L1
2 R7 C9
Error Amplifier Compensation
To stabilize the feedback loop dynamics the
error amplifier compensation is as follows:
fPOSPOLE1 and fNEGPOLE1 are necessary to cancel
out the zero created by the equivalent series
resistance (RLDOESR) of the output capacitor.
1
1
fPOLE1
fLDOZERO
2 106 C3
2 RLDOESR CLDO
1
For the component values shown in Figure 3, a
330pF capacitor provides about 30 of phase
margin and a bandwidth of approximately
90kHz on both regulators.
fZERO1
2 R3 C3
Where R3 and C3 are part of the compensation
network in Figure 3. A 6.8kΩ and 10nF
combination gives about 70 of phase margin
and bandwidth of about 35kHz for most load
conditions.
Layout Considerations
Careful PC board layout is important to
minimize ground bounce and noise. First, place
the main boost converter inductor, output diode
and output capacitor as close to the SW and
PGND pins as possible with wide traces. Then
place ceramic bypass capacitors near IN, IN2
and IN3 pins to the PGND pin. Keep the
charge-pump circuitry close to the IC with wide
traces. Place all FB resistive dividers close to
their respective FB pins. Separate GND and
PGND areas and connect them at one point as
close to the IC as possible. Avoid having
sensitive traces near the SW node and high
current lines. Refer to the MP1530 demo board
for an example of proper board layout.
Linear Regulator Compensation
The positive and negative regulators are
controlled by a transconductance amplifier and
a pass transistor. The DC gain of either LDO is
approximately 100dB with a slight dependency
on load current. The output capacitor (CLDO) and
resistance load (RLOAD) make-up the dominant
pole.
1
fLDOPOLE1
2 RLOAD CLDO
The pass transistor’s internal pole is about
100Hz to 300Hz. To compensate for the two
pole system and add more phase and gain
margin, a capacitor network can be added in
parallel with the high-side resistor.
For the positive linear regulator:
1
fPOSPOLE1
2 R9 R8 C7
1
fPOSZERO1
2 R9 C7
MP1530 Rev. 1.41
5/25/2011
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
13
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