MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
APPLICATION INFORMATION
Setting the Output Voltage-Large ESR Caps
considerable quiescent current loss while too
large R2 makes the FB noise sensitive. It is
recommended to choose a value within 5kꢀ-
50kꢀ for R2, using a comparatively larger R2
when Vo is low, etc.,1.05V, and a smaller R2
when Vo is high. And the value of R1 then is
determined as follow:
For applications that electrolytic capacitor or POS
capacitor with a controlled output of ESR is set
as output capacitors. The output voltage is set by
feedback resistors R1 and R2. As figure 8 shows.
R2
(11)
R1=
V
R2
FB(AVG)
-
(VOUT -VFB(AVG) ) R4 +R9
The VFB(AVG) is the average value on the FB,
VFB(AVG) varies with the Vin, Vo, and load
condition, etc., its value on the skip mode would
be lower than that of the PWM mode, which
means the load regulation is strictly related to the
Figure 8—Simplified Circuit of POS Capacitor
First, choose a value for R2. R2 should be
chosen reasonably, a small R2 will lead to
considerable quiescent current loss while too
large R2 makes the FB noise sensitive. It is
recommended to choose a value within 5kꢀ-
50kꢀ for R2, using a comparatively larger R2
when Vo is low,etc.,1.05V, and a smaller R2
when Vo is high. Then R1 is determined as follow
with the output ripple considered:
VFB(AVG). Also the line regulation is related to the
VFB(AVG) ,if one wants to gets a better load or line
regulation, a lower Vramp is suggested once it
meets equation 8.
For PWM operation, VFB(AVG) value can be
deduced from equation 12.
1
R1 //R2
V
= VREF + VRAMP
×
(12)
FB(AVG)
1
2
R1 //R2 +R9
VOUT
−
ΔVOUT − VREF
2
(10)
R1 =
R2
Usually, R9 is set to 0ꢀ, and it can also be set
following equation 13 for a better noise immunity.
It should also set to be 5 timers smaller than
R1//R2 to minimize its influence on Vramp.
VREF
ΔVOUT is the output ripple determined by equation
19.
1
R9 ≤
(13)
2π×C4 ×2F
SW
Using equation 11 to calculate the output voltage
can be complicated. To simplify the calculation of
R1 in equation 11, a DC-blocking capacitor Cdc
can be added to filter the DC influence from R4
and R9. Figure 10 shows a simplified circuit with
external ramp compensation and a DC-blocking
capacitor. With this capacitor, R1 can easily be
obtained by using equation 14 for PWM mode
operation.
Figure 9—Simplified Circuit of Ceramic
Capacitor
Setting the Output Voltage-Small ESR Caps
When low ESR ceramic capacitor is used in the
output, an external voltage ramp should be
added to FB through resistor R4 and capacitor
C4.The output voltage is influenced by ramp
voltage VRAMP besides R divider. The VRAMP can
be calculated as shown in equation 6, R2 should
be chosen reasonably, a small R2 will lead to
1
(VOUT − VREF − VRAMP
)
2
(14)
R1 =
R2
1
VREF + VRAMP
2
Cdc is suggested to be at least 10 times larger
than C4 for better DC blocking performance, and
MP1492 Rev. 1.1
3/13/2012
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