欢迎访问ic37.com |
会员登录 免费注册
发布采购

MP1492DS-LF-Z 参数 Datasheet PDF下载

MP1492DS-LF-Z图片预览
型号: MP1492DS-LF-Z
PDF下载: 下载PDF文件 查看货源
内容描述: [Switching Regulator, Current-mode, PDSO8, ROHS COMPLIANT, MS-012AA, SOIC-8]
分类和应用: 开关光电二极管
文件页数/大小: 18 页 / 448 K
品牌: MPS [ MONOLITHIC POWER SYSTEMS ]
 浏览型号MP1492DS-LF-Z的Datasheet PDF文件第6页浏览型号MP1492DS-LF-Z的Datasheet PDF文件第7页浏览型号MP1492DS-LF-Z的Datasheet PDF文件第8页浏览型号MP1492DS-LF-Z的Datasheet PDF文件第9页浏览型号MP1492DS-LF-Z的Datasheet PDF文件第11页浏览型号MP1492DS-LF-Z的Datasheet PDF文件第12页浏览型号MP1492DS-LF-Z的Datasheet PDF文件第13页浏览型号MP1492DS-LF-Z的Datasheet PDF文件第14页  
MP1492 – 2A, 4.2V-16V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER  
HS-FET deviates from its intended location and  
To realize the stability when no external ramp is  
used, usually the ESR value should be chosen  
as follow:  
produces jitter. It is necessary to understand that  
there is a relationship between a system’s  
stability and the steepness of the VFB ripple’s  
downward slope. The slope steepness of the VFB  
ripple dominates in noise immunity. The  
magnitude of the VFB ripple doesn’t directly affect  
the noise immunity directly.  
TSW  
TON  
2
+
0.7× π  
(3)  
RESR  
COUT  
TSW is the switching period.  
Ramp with small ESR Cap  
When the output capacitors are ceramic ones,  
the ESR ripple is not high enough to stabilize the  
system, and external ramp compensation is  
needed. Skip to application information section  
for design steps with small ESR caps.  
L
Vo  
Figure 3—Jitter in PWM Mode  
SW  
C4  
R4  
R9  
R1  
R2  
IR4  
IC4  
IFB  
Ceramic  
FB  
Figure 6—Simplified Circuit in PWM Mode  
with External Ramp Compensation  
Figure 4—Jitter in Skip Mode  
Ramp with Large ESR Cap  
In PWM mode, an equivalent circuit with HS-FET  
off and the use of an external ramp  
compensation circuit (R4, C4) is simplified in  
Figure 6. The external ramp is derived from the  
inductor ripple current. If one chooses C4, R9,  
R1 and R2 to meet the following condition:  
In the case of POSCAP or other types of  
capacitor with larger ESR is applied as output  
capacitor. The ESR ripple dominates the output  
ripple, and the slope on the FB is quite ESR  
related. Figure 5 shows an equivalent circuit in  
PWM mode with the HS-FET off and without an  
external ramp circuit. Turn to application  
information section for design steps with large  
ESR caps.  
1
1
5
R1 ×R2  
R1 + R2  
(4)  
<
×
+ R9  
2π×FSW ×C4  
Where:  
SW  
L
Vo  
IR4 = IC4 + IFB IC4  
(5)  
ESR  
POSCAP  
And the ramp on the VFB can then be estimated  
as:  
R1  
R2  
FB  
V VO  
R1 //R2  
IN  
(6)  
VRAMP  
=
×TON ×  
R4 ×C4  
R1 //R2 +R9  
The downward slope of the VFB ripple then  
follows  
Figure 5—Simplified Circuit in PWM Mode  
without External Ramp Compensation  
MP1492 Rev. 1.1  
3/13/2012  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
10