MP1039 – FULL BRIDGE CCFL CONTROLLER
Pin 18 (SW1), Pin 25 (SW2), C12, R9:
SW1 and SW2 pins are used to sense the
voltage at the output of the full bridge. They
also are the point of access for the output
dampers. SW1 and SW2 should make a Kelvin
connection to the sources of the top MOSFETs
and the drains of the bottom MOSFETs in the
output bridge.
Pin 11 (DBRT):
This pin is used for burst brightness control.
The DC voltage on this pin will control the burst
percentage on the output. The signal is filtered for
optimal operation. A voltage ranging from 0 to
1.4V on DBRT will correspond to a Burst Duty
Cycle of 100% to 10% respectively.
For direct Pulse Width Modulation of the burst
signal, connect BRS to VCC and connect DBRT
to a logic level PWM signal. Logic High is Burst
On and a logic Low is Burst Off.
The primary transformer current flows through
capacitor C12. Its value is typically 2.2µF. This
capacitor should be ceramic and has a ripple
current rating greater than the primary current.
It is more optimal to use two parallel 1µF
ceramic caps for minimal ESR losses. R9 is
used to ensure that the bridge outputs are at 0V
prior to startup. Typically R9 = 1kꢀ.
Pin 10 (BRS): C7, R6:
BRS is used to set the Burst frequency. C7 and
R6 will set the burst frequency and the
minimum burst time: tMIN. Set tMIN to achieve the
minimum required system
Pin 16 (BT1), Pin 23 (BT2), C8, C10:
BT1 and BT2 are the bias supplies for the level
shift of the upper MOSFETs. C8 and C10
should be 22nF and made of X7R ceramic
material.
brightness. Ensure that tMIN is long enough that
the lamp does not extinguish.
These values are determined as follows:
Select a Minimum Duty Cycle, DMIN, where:
Pin 19 (VCC1), Pin 26 (VCC2), C9, C11:
These capacitors bypass the 6V gate supply for
the bottom switches. They also supply power to
the MP1039. These pins should be bypassed
with a 0.47µF ceramic X7R capacitor.
DMIN = tMIN × fBurst
tFALL
DMIN
=
(
tFALL + tRISE
)
If operating in Free-Running mode:
Pin 13 (ENSYNC):
⎛
⎞
⎟
⎠
1
ENSYNC is a composite of the Enable and the
Burst Oscillator Synchronization function. This
pin will enable and disable the chip when the
enable function is used.
⎜
⎜
⎟
− 1 Vbg
DMIN
VP + VV
⎝
+
ξ
2
R6 =
Ib
To synchronize the Burst Oscillator to an
external signal, remove R6 from BRS pin and
apply a 1µs to 10µs pulse with a falling edge
trigger and a repetition rate of 200Hz. The Burst
Oscillator will then be synchronized with this
signal and start a burst on its falling edge.
⎛
⎞
1
⎜
⎜
⎟
R6 ~ 21.16k
− 1 + 21.43k
⎟
DMIN
⎝
⎠
For DMIN = 0.1 and R6 = 212k
1− DMIN
C7 =
Pin 14 (LSYNC):
The lamp frequency can be externally
synchronized by applying a signal to this pin.
fb × R6 × γ
The synchronization clock must be greater than
the frequency f0 set by the SWSET pin, but no
greater than 1.4x the value of f0.
MP1039 Rev. 1.1
9/24/2007
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