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HR1001A 参数 Datasheet PDF下载

HR1001A图片预览
型号: HR1001A
PDF下载: 下载PDF文件 查看货源
内容描述: [Enhanced LLC Controller with Adaptive Dead-Time Control]
分类和应用:
文件页数/大小: 25 页 / 1407 K
品牌: MPS [ MONOLITHIC POWER SYSTEMS ]
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HR1001A – ENHANCED LLC CONTROLLER  
PIN FUNCTIONS (continued)  
Pin #  
Name Description  
Input voltage sense and brown in/out protection. If the voltage on BO is over 2.3V, the  
IC enables the gate driver. If the voltage on BO is below 1.81V, the IC is disabled.  
7
BO  
IC latch off. When the voltage on LATCH exceeds 1.85V, the IC shuts down and lowers its  
8
9
LATCH bias current to its near pre-startup level. LATCH is reset when the voltage on VCC is  
discharged below its UVLO threshold. Connect LATCH to GND if the function is not used.  
Half-bridge dv/dt sense. In order to detect the dv/dt of the half-bridge, a high-voltage  
HBVS capacitor is connected between SW and HBVS. The dv/dt current through HVBS is used to  
adjust the dead-time adaptively between the high-side gate and the low-side gate.  
Ground. Current return for both the low-side gate-driver and the IC bias. Connect all  
10  
GND  
external ground connections with a trace to GND, one for signals and a second for pulsed  
current return.  
Low-side gate driver output. The driver is capable of a 0.8A source/sink peak current to  
drive the lower MOSFET of the half-bridge. LG is pulled to GND during UVLO.  
11  
12  
13  
14  
LG  
VCC  
NC  
Supply voltage. VCC supplies both the IC bias and the low-side gate driver. A small  
bypass capacitor (e.g., 0.1µF) is helpful to get a clean bias voltage for the IC signal.  
High-voltage spacer. No internal connection. It isolates the high-voltage pin and eases  
compliance with safety regulations (creepage-distance) on the PCB.  
High-side switch source. Current return for the high-side gate drive current. SW requires  
careful layout to avoid large spikes below ground.  
SW  
High-side floating gate driver output. HG is capable of a 0.8A source/sink peak current  
to drive the upper MOSFET of the half-bridge. An internal resistor connected to SW  
ensures that HG does not float during UVLO.  
15  
16  
HG  
Bias for floating voltage supply of high-side gate driver. Connect a bootstrap capacitor  
between BST and SW. This capacitor is charged by an internal bootstrap diode driven in-  
phase with the low-side gate drive.  
BST  
HR1001A Rev.1.1  
3/14/2016  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2016 MPS. All Rights Reserved.  
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