HR1001A – ENHANCED LLC CONTROLLER
PIN FUNCTIONS
Pin # Name Description
Soft-start. Connect an external capacitor from SS to GND and a resistor to FSET to set the
maximum oscillator frequency and the time constant for the frequency shift during start-up. An
internal switch discharges the capacitor when the chip turns off (VCC < UVLO, BO < 1.81V or
> 5.5V, LATCH > 1.85V, CS >1.5V, TIMER > 2V, thermal shutdown) to guarantee soft-start.
1
SS
Period between over-current and shutdown. Connect a capacitor and a resistor from
TIMER to GND to set both the maximum duration from an over-current condition before the IC
stops switching, and the delay before the IC resumes switching. Each time the voltage on CS
exceeds 0.78V, an internal 130µA source charges the capacitor; an external resistor
discharges this capacitor slowly. If the voltage on TIMER reaches 2V, the soft-start capacitor
discharges completely, raising its switching frequency to its maximum value. The 130µA
source remains on. When the voltage exceeds 3.5V, the IC stops switching and the internal
current source turns off, then the voltage decays. The IC enters soft start when the voltage
drops below 0.28V. This converter works intermittently with very low average input power
under short-circuit conditions.
2
TIMER
Time set. An internal current source programmed by an external network connected to FSET
charges and discharges a capacitor connected to GND. This determines the converter’s
switching frequency.
Switching frequency set. FSET provides a precise 2V reference. A resistor connected from
FSET to GND defines a current that sets the minimum oscillator frequency. Connect the
phototransistor of an optocoupler to FSET through a resistor to close the feedback loop that
modulates the oscillator frequency. It regulates the converter’s output voltage. The value of
this resistor sets the maximum operating frequency. An R-C series connected from FSET to
GND sets the frequency shift at start-up to prevent excessive inrush energy.
3
4
CT
FSET
Burst mode operation threshold. BURST senses the voltage related to the feedback
control, which is compared to an internal reference (1.23V). When the voltage on BURST is
lower than this reference, the IC enters an idle state and reduces its quiescent current. When
the feedback drives BURST above 1.26V (30mV hysteresis), the chip resumes switching. A
soft start is not invoked. This function enables burst mode operation when the load falls below
a programmed level, determined by connecting an appropriate resistor to the optocoupler to
FSET (see Functional Block Diagram). Connect BURST to FSET if burst mode is not used.
5
BURST
Current sense of half-bridge. CS uses a sense resistor or a capacitive divider to sense the
primary current. CS has the following functions:
•
Over-current regulation: As the voltage exceeds a 0.78V threshold, the soft-start
capacitor on SS discharges internally. The frequency increases, limiting the power
throughput. Under an output short circuit, this normally results in a nearly constant peak
primary current . TIMER limits the duration of this condition.
•
Over-current protection: If the current continues to build despite the frequency increase,
when Vcs>1.5V, the IC stops switching immediately and TIMER continues to be
charged. Once the voltage on TIMER exceeds 3.5V, the IC turns off the internal charge
current and the voltage on TIMER decays. The IC re-enters soft start when the voltage
falls below 0.28V. This is the auto-recovery operation in an over-current condition.
Capacitive mode protection: The moment LG turns off, CS is compared to the VCSNR
CMP threshold. If Vcs > VCSNR, it blocks the HG gate turning on until the slope is
detected, or the CMP timer is complete. The moment HG turns off, CS is compared to
the VCSPR CMP threshold. If Vcs < VCSPR, it blocks the low-side gate turning on until the
slope is detected, or the CMP timer is complete. If a capacitive mode status is detected,
SS is not discharged immediately; there is a 1µs delay. After the blanking delay, SS is
discharged if the fault condition in capacitive mode remains. It avoids the influence of CS
noise effectively. Connect CS to GND if the function is not used.
6
CS
•
HR1001A Rev.1.1
3/14/2016
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
10
MPS [ MONOLITHIC POWER SYSTEMS ]
