References
7.6 References
Semiconductor Equipment and Materials International
805 East Middlefield Rd
(415) 964-5111
Mountain View, CA 94043
MIL-SPEC and EIA/JESD (JEDEC) specifications
(Available from Global Engineering Documents)
800-854-7179 or
303-397-7956
JEDEC Specifications
http://www.jedec.org
1. 1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA
Within anAutomotive Engine Controller Module,” Proceedings of SemiTherm, San
Diego, 1998, pp. 47–54.
2. 2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board
Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of
SemiTherm, San Diego, 1999, pp. 212–220.
Part VIII Layout Practices
Each VDD pin on the MPC860 should be provided with a low-impedance path to the board’s
supply. Each GND pin should likewise be provided with a low-impedance path to ground.
The power supply pins drive distinct groups of logic on chip. The VDD power supply should
be bypassed to ground using at least four 0.1 µF-bypass capacitors located as close as
possible to the four sides of the package. The capacitor leads and associated printed circuit
traces connecting to chip VDD and GND should be kept to less than half an inch per
capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and
GND planes.
All output pins on the MPC860 have fast rise and fall times. Printed circuit (PC) trace
interconnection length should be minimized in order to minimize undershoot and
reflections caused by these fast output switching times. This recommendation particularly
applies to the address and data busses. Maximum PC trace lengths of 6 inches are
recommended. Capacitance calculations should consider all device loads as well as
parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing
becomes especially critical in systems with higher capacitive loads because these loads
create higher transient currents in the VCC and GND circuits. Pull up all unused inputs or
signals that will be inputs during reset. Special care should be taken to minimize the noise
levels on the PLL supply pins.
Part IX Bus Signal Timing
Table 9-6 provides the bus operation timing for the MPC860 at 33, 40, 50, and 66 MHz.
The maximum bus speed supported by the MPC860 is 66 MHz. Higher-speed parts must
be operated in half-speed bus mode (for example, an MPC860 used at 80 MHz must be
configured for a 40 MHz bus).
MOTOROLA
MPC860 Family Hardware Specifications
13
MOTOROLA [ MOTOROLA ]
