Freescale Semiconductor, Inc.
Advance Information — 68HC(9)12D60
Section 6. Bus Control and Input/Output
6.1 Contents
6.2
6.3
6.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Detecting Access Type from External Signals . . . . . . . . . . . . .87
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
6.2 Introduction
Internally the 68HC(9)12D60 has full 16-bit data paths, but depending
upon the operating mode and control registers, the external multiplexed
bus may be 8 or 16 bits. There are cases where 8-bit and 16-bit
accesses can appear on adjacent cycles using the LSTRB signal to
indicate 8- or 16-bit data.
It is possible to have a mix of 8 and 16 bit peripherals attached to the
external multiplexed bus, using the NDRF bit in the MISC register while
in expanded wide modes.
6.3 Detecting Access Type from External Signals
The external signals LSTRB, R/W, and A0 can be used to determine the
type of bus access that is taking place. Accesses to the internal RAM
module are the only type of access that produce LSTRB = A0 = 1,
because the internal RAM is specifically designed to allow misaligned
16-bit accesses in a single cycle. In these cases the data for the address
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
Bus Control and Input/Output
87
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