Freescale Semiconductor, Inc.
Enhanced Capture Timer
Timer Registers
The action of latching can be programmed to be periodic or only once.
14.4 Timer Registers
Input/output pins default to general-purpose I/O lines until an internal
function which uses that pin is specifically enabled. The timer overrides
the state of the DDR to force the I/O state of each associated port line
when an output compare using a port line is enabled. In these cases the
data direction bits will have no affect on these lines.
When a pin is assigned to output an on-chip peripheral function, writing
to this PORTT bit does not affect the pin but the data is stored in an
internal latch such that if the pin becomes available for general-purpose
output the driven level will be the last value written to the PORTT bit.
Bit 7
IOS7
0
6
IOS6
0
5
IOS5
0
4
IOS4
0
3
IOS3
0
2
IOS2
0
1
IOS1
0
Bit 0
IOS0
0
RESET:
TIOS — Timer Input Capture/Output Compare Select
$0080
Read or write anytime.
IOS[7:0] — Input Capture or Output Compare Channel Configuration
0 = The corresponding channel acts as an input capture
1 = The corresponding channel acts as an output compare.
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
Enhanced Capture Timer
207
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