4.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS
Replace Figure 10-2 on page 10-6 with Figure 7.
DRIVE
TO 2.4 V
2.0 V
2.0 V
0.8 V
CLK
0.8 V
A
DRIVE TO
0.5 V
B
2.0 V
0.8 V
2.0 V
0.8 V
VALID
OUTPUT
VALID
OUTPUT
OUTPUTS(1) CLK
OUTPUTS(2) CLK
A
n
n + 1
B
2.0 V
0.8 V
2.0 V
0.8 V
VALID
OUTPUT
VALID
OUTPUT
n
n+1
C
D
DRIVE TO
2.4 V
2.0 V
0.8 V
2.0 V
0.8 V
VALID
INPUT
INPUTS(3) CLK
DRIVE TO
0.5 V
C
D
DRIVE
2.0 V
0.8 V
2.0 V
0.8 V
TO 2.4 V
VALID
INPUT
INPUTS(4) CLK
ALL SIGNALS(5)
DRIVE
TO 0.5 V
2.0 V
0.8 V
E
F
2.0 V
0.8 V
NOTES:
1. This output timing is applicable to all parameters specified relative to the rising edge of the clock.
2. This output timing is applicable to all parameters specified relative to the falling edge of the clock.
3. This input timing is applicable to all parameters specified relative to the rising edge of the clock.
4. This input timing is applicable to all parameters specified relative to the falling edge of the clock.
5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal.
LEGEND:
A. Maximum output delay specification.
B. Minimum output hold time.
C. Minimum input setup time specification.
D. Minimum input hold time specification.
E. Signal valid to signal valid specification (maximum or minimum).
F. Signal valid to signal invalid specification (maximum or minimum).
Figure 7. Drive Levels and Test Points for AC Specifications - applies to all parts
M68000 USER’S MANUAL ADDENDUM MOTOROLA
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