address bus. (The breakpoint acknowledge code of %0000 is placed on ADDR[19:16],
the breakpoint number value of %111 is placed on ADDR[4:2], and ADDR1 is set to 1,
indicating a hardware breakpoint.)
The external breakpoint circuitry decodes the function code and address lines, places
an instruction word on the data bus, and asserts BERR. The CPU then performs hard-
ware breakpoint exception processing: it acquires the number of the hardware break-
point exception vector, computes the vector address from this number, loads the
content of the vector address into the PC, and jumps to the exception handler routine
at that address. If the external device asserts DSACK rather than BERR, the CPU ig-
nores the breakpoint and continues processing.
When BKPT assertion is synchronized with an instruction prefetch, processing of the
breakpoint exception occurs at the end of that instruction. The prefetched instruction
is “tagged” with the breakpoint when it enters the instruction pipeline, and the break-
point exception occurs after the instruction executes. If the pipeline is flushed before
the tagged instruction is executed, no breakpoint occurs. When BKPT assertion is syn-
chronized with an operand fetch, exception processing occurs at the end of the instruc-
tion during which BKPT is latched.
4
Refer to the CPU32 Reference Manual (CPU32RM/AD) and the SIM Reference Man-
ual (SIMRM/AD) for additional information.
MOTOROLA
4-28
SYSTEM INTEGRATION MODULE
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
