4.4.1 Bus Signals
The address bus provides addressing information to external devices. The data bus
transfers 8-bit and 16-bit data between the MCU and external devices. Strobe signals,
one for the address bus and another for the data bus, indicate the validity of an ad-
dress and provide timing information for data.
Control signals indicate the beginning of each bus cycle, the address space it is to take
place in, the size of the transfer, and the type of cycle. External devices decode these
signals and respond to transfer data and terminate the bus cycle. The EBI operates in
an asynchronous mode for any port width.
4.4.1.1 Address Bus
Bus signals ADDR[23:0] define the address of the byte (or the most significant byte)
to be transferred during a bus cycle. The MCU places the address on the bus at the
beginning of a bus cycle. The address is valid while AS is asserted.
4.4.1.2 Address Strobe
Address strobe AS is a timing signal that indicates the validity of an address on the
address bus and of many control signals. It is asserted one-half clock after the begin-
ning of a bus cycle.
4
4.4.1.3 Data Bus
Signals DATA[15:0 form a bidirectional, nonmultiplexed parallel bus that transfers data
to or from the MCU. A read or write operation can transfer eight or sixteen bits of data
in one bus cycle. During a read cycle, the data is latched by the MCU on the last falling
edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus are
driven, regardless of the port width or operand size. The MCU places the data on the
data bus one-half clock cycle after AS is asserted in a write cycle.
4.4.1.4 Data Strobe
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an
external device to place data on the bus. DS is asserted at the same time as AS during
a read cycle. For a write cycle, DS signals an external device that data on the bus is
valid. The MCU asserts DS one full clock cycle after the assertion of AS during a write
cycle.
4.4.1.5 Read/Write Signal
The read/write signal (R/W determines the direction of the transfer during a bus cycle.
This signal changes state, when required, at the beginning of a bus cycle, and is valid
while AS is asserted. R/W only transitions when a write cycle is preceded by a read
cycle or vice versa. The signal may remain low for two consecutive write cycles.
4.4.1.6 Size Signals
Size signals (SIZ[1:0]) indicate the number of bytes remaining to be transferred during
an operand cycle. They are valid while the address strobe (AS) is asserted. Table 4-
10 shows SIZ0 and SIZ1 encoding.
MOTOROLA
4-18
SYSTEM INTEGRATION MODULE
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
