or
System Clock
SPBR = ----------------------------------------------------------------------------------------
(2 × SCK) × (Baud Rate Desired)
Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled
and assumes its inactive state value.
The DSCK field in command RAM determines the delay period from chip-select asser-
tion until the leading edge of the serial clock. The DSCKL field in SPCR1 determines
the period of delay before the assertion of SCK. The following expression determines
the actual delay before SCK:
DSCKL
PCS to SCK Delay = ------------------------------------------------------------------
System Clock Frequency
where DSCKL equals {1, 2, 3,..., 127}.
When DSCK equals zero, DSCKL is not used. Instead, the PCS valid-to-SCK transi-
tion is one-half the DSCK period.
There are two transfer length options. The user can choose a default value of eight
bits, or a programmed value of eight to sixteen bits, inclusive. The programmed value
must be written into the BITS field in SPCR0. The BITSE field in command RAM de-
termines whether the default value (BITSE = 0) or the BITS value (BITSE = 1) is used.
Table 6-3 shows BITS field encoding.
6
Table 6-3 BITS Encoding
BITS
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Bits per Transfer
16
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8
9
10
11
12
13
14
15
Delay after transfer can be used to provide a peripheral deselect interval. A delay can
also be inserted between consecutive transfers to allow serial A/D converters to com-
plete conversion. There are two transfer delay options. The user can choose to delay
a standard period after serial transfer is complete or can specify a delay period. Writing
a value to the DTL field in SPCR1 specifies a delay period. The DT bit in command
RAM determines whether the standard delay period (DT = 0) or the specified delay pe-
MOTOROLA
6-18
QUEUED SERIAL MODULE
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
