Normally, the SPI bus performs synchronous bidirectional transfers. The serial clock
on the SPI bus master supplies the clock signal (SCK) to time the transfer of data. Four
possible combinations of clock phase and polarity can be specified by the CPHA and
CPOL bits in SPCR0.
Data is transferred with the most significant bit first. The number of bits transferred per
command defaults to eight, but can be set to any value from eight to sixteen bits by
writing a value into the BITSE field in command RAM.
Typically, SPI bus outputs are not open-drain unless multiple SPI masters are in the
system. If needed, the WOMQ bit in SPCR0 can be set to provide wired-OR, open-
drain outputs. An external pull-up resistor should be used on each output line. WOMQ
affects all QSPI pins regardless of whether they are assigned to the QSPI or used as
general-purpose I/O.
6.3.5.1 Master Mode
Setting the MSTR bit in SPCR0 selects master mode operation. In master mode, the
QSPI can initiate serial transfers, but cannot respond to externally initiated transfers.
When the slave select input of a device configured for master mode is asserted, a
mode fault occurs.
6
Before QSPI operation is initiated, QSM register PQSPAR must be written to assign
necessary pins to the QSPI. The pins necessary for master mode operation are MISO
and MOSI, SCK, and one or more of the chip-select pins. MISO is used for serial data
input in master mode, and MOSI is used for serial data output. Either or both may be
necessary, depending on the particular application. SCK is the serial clock output in
master mode.
Before master mode operation is initiated, QSM register DDRQS must be written to
direct the data flow on the QSPI pins used. Configure the SCK, MOSI and appropriate
chip-select pins PCS[3:0]/SS as outputs. The MISO pin must be configured as an in-
put.
After pins are assigned and configured, write appropriate data to the command queue.
If data is to be transmitted, write the data to transmit RAM. Initialize the queue pointers
as appropriate.
Data transfer is synchronized with the internally-generated serial clock (SCK). Control
bits, CPHA and CPOL, in SPCR0, control clock phase and polarity. Combinations of
CPHA and CPOL determine upon which SCK edge to drive outgoing data from the
MOSI pin and to latch incoming data from the MISO pin.
Baud rate is selected by writing a value from 2 to 255 into the SPBR field in SPCR0.
The QSPI uses a modulus counter to derive SCK baud rate from the MCU system
clock.
The following expressions apply to SCK baud rate:
System Clock
SCK Baud Rate = ------------------------------------
2 × SPBR
MC68331
QUEUED SERIAL MODULE
MOTOROLA
6-17
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
